A Graph Model for Investigating Memory Consistency. - Weiwu Hu (ICPADS, 1994)

Event Ordering Condition for Correct Executions in Shared-Memory Systems. - Weiwu Hu; Peisu Xia (ISPAN, 1996)

Out-of-order execution in sequentially consistent shared-memory systems. - Weiwu Hu; Peisu Xia (SIGARCH Comput. Archit. News, 1997)

An innovative implementation for directory-based cache coherence in shared memory multiprocessors. - Weisong Shi; Weiwu Hu; Ming Zhu (SIGARCH Comput. Archit. News, 1997)

An Interaction of Coherence Protocols and Memory Consistency Models in DSM Systems. - Weisong Shi; Weiwu Hu; Zhimin Tang (ACM SIGOPS Oper. Syst. Rev., 1997)

A framework of memory consistency models. - Weiwu Hu; Weisong Shi; Zhimin Tang (J. Comput. Sci. Technol., 1998)

A lock-based cache coherence protocol for scope consistency. - Weiwu Hu; Weisong Shi; Zhimin Tang; Ming Li (J. Comput. Sci. Technol., 1998)

Out-of-order execution in sequentially consistent shared-memory systems: Theory and experiments. - Weiwu Hu; Peisu Xia (J. Comput. Sci. Technol., 1998)

Write Detection in Home-Based Software DSMs. - Weiwu Hu; Weisong Shi; Zhimin Tang (Euro-Par, 1999)

Evaluation of the JIAJIA Software DSM System on High Performance Computer Architectures. - M. Rasit Eskicioglu; T. Anthony Marsland; Weiwu Hu; Weisong Shi (HICSS, 1999)

JIAJIA: A Software DSM System Based on a New Cache Coherence Protocol. - Weiwu Hu; Weisong Shi; Zhimin Tang (HPCN Europe, 1999)

Adaptive Write Detection in Home-based Software DSMs. - Weiwu Hu; Weisong Shi; Zhimin Tang (HPDC, 1999)

Dynamic Task Migration in Home-based Software DSM Systems. - Weisong Shi; Weiwu Hu; Zhimin Tang; M. Rasit Eskicioglu (HPDC, 1999)

Reducing System Overheads in Home-based Software DSMs. - Weiwu Hu; Weisong Shi; Zhimin Tang (IPPS/SPDP, 1999)

Where does the time go in software DSMs? - Experiences with JIAJIA. - Weisong Shi; Weiwu Hu; Zhimin Tang (J. Comput. Sci. Technol., 1999)

A New Home-Based Software DSM Protocol for SMP Clusters. - Weiwu Hu; Fuxin Zhang; Haiming Liu (Euro-Par, 2000)

Communication with Threads in Software DSM. - Weiwu Hu; Gang Shi; Fuxin Zhang (CLUSTER, 2001)

A Comparison of Two Strategies of Dynamic Data Prefetching in Software DSM. - Haiming Liu; Weiwu Hu (IPDPS, 2001)

Optimizing Home-Based Software DSM Protocols. - Weiwu Hu; Weisong Shi; Zhimin Tang (Clust. Comput., 2001)

Dynamic Data Prefetching in Home-Based Software DSMs. - Weiwu Hu; Fuxin Zhang; Haiming Liu (J. Comput. Sci. Technol., 2001)

A shared virtual memory network with fast remote direct memory access and message passing. - Gang Shi; Mingchang Hu; Hongda Yin; Weiwu Hu; Zhimin Tang (CLUSTER, 2004)

A Memory Bandwidth Effective Cache Store Miss Policy. - Hou Rui; Fuxin Zhang; Weiwu Hu (Asia-Pacific Computer Systems Architecture Conference, 2005)

A novel design of leading zero anticipation circuit with parallel error detection. - Ge Zhang 007; Zichu Qi; Weiwu Hu (ISCAS (1), 2005)

Microarchitecture of the Godson-2 Processor. - Weiwu Hu; Fuxin Zhang; Zusong Li (J. Comput. Sci. Technol., 2005)

Processor Directed Dynamic Page Policy. - Dandan Huan; Zusong Li; Weiwu Hu; Zhiyong Liu (Asia-Pacific Computer Systems Architecture Conference, 2006)

A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors. - Hou Rui; Longbing Zhang; Weiwu Hu (Euro-Par, 2006)

Microarchitecture and Performance Analysis of Godson-2 SMT Processor. - Zusong Li; Xianchao Xu; Weiwu Hu; Zhimin Tang (ICCD, 2006)

High Performance General-Purpose Microprocessors: Past and Future. - Weiwu Hu; Rui Hou; Jun-Hua Xiao; Long-Bin Zhang (J. Comput. Sci. Technol., 2006)

Parallel Error Detection for Leading Zero Anticipation. - Ge Zhang 007; Weiwu Hu; Zichu Qi (J. Comput. Sci. Technol., 2006)

Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs. - Hongbo Zeng; Kun Huang; Ming Wu; Weiwu Hu (Asia-Pacific Computer Systems Architecture Conference, 2007)

CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors. - Shijian Zhang; Weiwu Hu (ATS, 2007)

An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects. - Jun Wang; Ge Zhang 007; Weiwu Hu (ISCAS, 2007)

Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology. - Weiwu Hu; Ji-Ye Zhao; Shi-Qiang Zhong; Xu Yang; Elio Guidetti; Chris Wu (J. Comput. Sci. Technol., 2007)

Accelerating sequential programs on Chip Multiprocessors via Dynamic Prefetching Thread. - Hou Rui; Longbing Zhang; Weiwu Hu (Microprocess. Microsystems, 2007)

A High Speed CMOS Transmitter and Rail-to-Rail Receiver. - Feng Zhang 014; Zongren Yang; Wei Feng; Hao Cui; Lingyi Huang; Weiwu Hu (DELTA, 2008)

Testing content addressable memories using instructions and march-like algorithms. - Lin Ma; Yunji Chen; Menghao Su; Zichu Qi; Heng Zhang; Weiwu Hu (ICECS, 2008)

An interconnect-aware power efficient cache coherence protocol for CMPs. - Hongbo Zeng; Jun Wang; Ge Zhang 007; Weiwu Hu (IPDPS, 2008)

A synchronized variable frequency clock scheme in chip multiprocessors. - Qifei Fan; Ge Zhang 007; Weiwu Hu (ISCAS, 2008)

Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor. - Shijian Zhang; Weiwu Hu (PRDC, 2008)

Making Effective Decisions in Computer Architects' Real-World: Lessons and Experiences with Godson-2 Processor Designs. - Weiwu Hu; Jian Wang (J. Comput. Sci. Technol., 2008)

Chip Multithreaded Consistency Model. - Zusong Li; Dandan Huan; Weiwu Hu; Zhimin Tang (J. Comput. Sci. Technol., 2008)

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. - Zichu Qi; Hui Liu; Xiangku Li; Da Wang; Yinhe Han 001; Huawei Li 001; Weiwu Hu (Asian Test Symposium, 2009)

Fast complete memory consistency verification. - Yunji Chen; Yi Lv; Weiwu Hu; Tianshi Chen 002; Haihua Shen; Pengyu Wang; Hong Pan (HPCA, 2009)

Efficient binary translation system with low hardware cost. - Weiwu Hu; Qi Liu; Jian Wang; Songsong Cai; Menghao Su; Xiaoyu Li (ICCD, 2009)

A case study of improving at-speed testing coverage of a gigahertz microprocessor. - Zichu Qi; Hui Liu; Xiangku Li; Jun Xu; Weiwu Hu (ICECS, 2009)

Measuring and Compensating for Process Mismatch-induced, Reference Spurs in Phase-locked Loops using a Sub-sampled DSP. - Zhuo Gao; D. Kesharwani; Patrick Chiang 001; Weiwu Hu (ISCAS, 2009)

Global Clock, Physical Time Order and Pending Period Analysis in Multiprocessor Systems - Yunji Chen; Tianshi Chen 002; Weiwu Hu (CoRR, 2009)

Godson-3: A Scalable Multicore RISC Processor with x86 Emulation. - Weiwu Hu; Jian Wang; Xiang Gao; Yunji Chen; Qi Liu; Guojie Li (IEEE Micro, 2009)

On-the-Fly Reduction of Stimuli for Functional Verification. - Qi Guo 001; Tianshi Chen 002; Haihua Shen; Yunji Chen; Weiwu Hu (Asian Test Symposium, 2010)

A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only). - Huandong Wang; Xiang Gao; Yunji Chen; Dan Tang; Weiwu Hu (FPGA, 2010)

DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance. - Dan Tang; Yungang Bao; Weiwu Hu; Mingyu Chen 001 (HPCA, 2010)

LReplay: a pending period based deterministic replay scheme. - Yunji Chen; Weiwu Hu; Tianshi Chen 002; Ruiyang Wu 001 (ISCA, 2010)

Optimizing power and throughput for m-out-of-n encoded asynchronous circuits. - Jun Xu; Ge Zhang 007; Weiwu Hu (ISQED, 2010)

Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power. - Zichu Qi; Qi Guo 001; Ge Zhang 007; Xiangku Li; Weiwu Hu (VLSI Design, 2010)

System Architecture of Godson-3 Multi-Core Processors. - Xiang Gao; Yunji Chen; Huandong Wang; Dan Tang; Weiwu Hu (J. Comput. Sci. Technol., 2010)

Empirical design bugs prediction for verification. - Qi Guo 001; Tianshi Chen 002; Haihua Shen; Yunji Chen; Yue Wu; Weiwu Hu (DATE, 2011)

Alpha Compression with Variable Data Formats. - Yifei Jiang; Mindan Gui; Shuai Chen; Weiwu Hu (Eurographics (Short Papers), 2011)

Effective and Efficient Microprocessor Design Space Exploration Using Unlabeled Design Configurations. - Qi Guo 001; Tianshi Chen 002; Yunji Chen; Zhi-Hua Zhou; Weiwu Hu; Zhiwei Xu 002 (IJCAI, 2011)

Godson-3B: A 1GHz 40W 8-core 128GFLOPS processor in 65nm CMOS. - Weiwu Hu; Ru Wang; Yunji Chen; Bao-Xia Fan; Shi-Qiang Zhong; Xiang Gao; Zichu Qi; Xu Yang (ISSCC, 2011)

Brief announcement: program regularization in verifying memory consistency. - Lei Li; Tianshi Chen 002; Yunji Chen; Ling Li 001; Cheng Qian; Weiwu Hu (SPAA, 2011)

The Godson Processors: Its Research, Development, and Contributions. - Weiwu Hu; Yan-Ping Gao; Tianshi Chen 002; Jun-Hua Xiao (J. Comput. Sci. Technol., 2011)

An FFT Performance Model for Optimizing General-Purpose Processor Architecture. - Ling Li 001; Yunji Chen; Dao-Fu Liu; Cheng Qian; Weiwu Hu (J. Comput. Sci. Technol., 2011)

Design for Testability Features of Godson-3 Multicore Microprocessor. - Zichu Qi; Hui Liu; Xiangku Li; Weiwu Hu (J. Comput. Sci. Technol., 2011)

Physical Implementation of the Eight-Core Godson-3B Microprocessor. - Ru Wang; Bao-Xia Fan; Liang Yang; Yan-Ping Gao; Dong Liu; Bin Xiao 006; Jiang-Mei Wang; Yifu Zhang; Hong Wang; Weiwu Hu (J. Comput. Sci. Technol., 2011)

Sinusoidal Clock Sampling for Multigigahertz ADCs. - Rui Bai 001; Jingguang Wang; Lingli Xia; Feng Zhang 014; Zongren Yang; Weiwu Hu; Patrick Chiang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Statistical performance comparisons of computers. - Tianshi Chen 002; Yunji Chen; Qi Guo 001; Olivier Temam; Yue Wu; Weiwu Hu (HPCA, 2012)

Linear Time Memory Consistency Verification. - Weiwu Hu; Yunji Chen; Tianshi Chen 002; Cheng Qian; Lei Li (IEEE Trans. Computers, 2012)

Program Regularization in Memory Consistency Verification. - Yunji Chen; Lei Li; Tianshi Chen 002; Ling Li 001; Lei Wang; Xiaoxue Feng; Weiwu Hu (IEEE Trans. Parallel Distributed Syst., 2012)

A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS. - Shuai Chen; Hao Li 047; Liqiong Yang; Zongren Yang; Weiwu Hu; Patrick Yin Chiang (CICC, 2013)

Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor. - Weiwu Hu; Yifu Zhang; Liang Yang; Bao-Xia Fan; Yunji Chen; Shi-Qiang Zhong; Huandong Wang; Zichu Qi; Pengyu Wang; Xiang Gao; Xu Yang; Bin Xiao 006; et al. (ISSCC, 2013)

Microarchitectural design space exploration made fast. - Qi Guo 001; Tianshi Chen 002; Yunji Chen; Ling Li 001; Weiwu Hu (Microprocess. Microsystems, 2013)

Deterministic Replay Using Global Clock. - Yunji Chen; Tianshi Chen 002; Ling Li 001; Ruiyang Wu 001; Dao-Fu Liu; Weiwu Hu (ACM Trans. Archit. Code Optim., 2013)

LDet: Determinizing Asynchronous Transfer for Postsilicon Debugging. - Yunji Chen; Tianshi Chen 002; Ling Li 001; Lei Li; Liang Yang; Menghao Su; Weiwu Hu (IEEE Trans. Computers, 2013)

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS. - Hao Li 047; Shuai Chen; Liqiong Yang; Rui Bai 001; Weiwu Hu; Freeman Y. Zhong; Samuel Palermo; Patrick Yin Chiang (VLSIC, 2014)

Auxiliary stream for optimizing memory access of video decoders. - Shaoli Liu; Ling Li 001; Yunji Chen; Weiwu Hu (Sci. China Inf. Sci., 2014)

An 8-Core MIPS-Compatible Processor in 32/28 nm Bulk CMOS. - Weiwu Hu; Liang Yang; Bao-Xia Fan; Huandong Wang; Yunji Chen (IEEE J. Solid State Circuits, 2014)

Pre-Silicon Bug Forecast. - Qi Guo 001; Tianshi Chen 002; Yunji Chen; Rui Wang 022; Huanhuan Chen; Weiwu Hu; Guoliang Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

HERMES: a fast cross-ISA binary translator with post-optimization. - Xiaochun Zhang; Qi Guo 001; Yunji Chen; Tianshi Chen 002; Weiwu Hu (CGO, 2015)

An introduction to CPU and DSP design in China. - Weiwu Hu; Yifu Zhang; Jie Fu (Sci. China Inf. Sci., 2016)