A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. - Xingjun Wu; Hongyi Chen; Yihe Sun; Weixin Gai (J. VLSI Signal Process., 2003)

Design Consideration of 6.25 Gbps Signaling for High-Performance Server. - Jian Hong Jiang; Weixin Gai; Akira Hattori; Yasuo Hidaka; Takeshi Horie; Yoichi Koyanagi; Hideki Osone (ASP-DAC, 2007)

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. - Yasuo Hidaka; Weixin Gai; Akira Hattori; Takeshi Horie; Jian Jiang; Kouichi Kanda; Yoichi Koyanagi; Satoshi Matsubara; Hideki Osone (ISSCC, 2007)

A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. - Yasuo Hidaka; Weixin Gai; Takeshi Horie; Jian Hong Jiang; Yoichi Koyanagi; Hideki Osone (ISSCC, 2009)

A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. - Yasuo Hidaka; Weixin Gai; Takeshi Horie; Jian Hong Jiang; Yoichi Koyanagi; Hideki Osone (IEEE J. Solid State Circuits, 2009)

A 2.7-GHz digitally-controlled ring oscillator with supply sensitivity of 0.0014%-fDCO/1%-VDD using digital current-regulated tuning. - Te Han; Weixin Gai (ISCAS, 2013)

A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL. - Bohan Wu; Weixin Gai; Te Han (ISCAS, 2013)

SSC tracking analysis and a deeper-SSC estimator. - Yaming Zhang; Weixin Gai (ISCAS, 2013)

A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis. - Jincai Liu; Weixin Gai; Liangxiao Tang (ISCAS, 2015)

A 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis. - Yang Wang; Weixin Gai (ISCAS, 2015)

A 1.27mW 20Gbps 1: 16 DEMUX with a symmetrical-edge-delay sense amplifier. - Shihao Li; Weixin Gai; Xiao Xiang; Liangxiao Tang; Jichao Huang; Tong Zhao; Xiaoting Zhi (ISCAS, 2016)

PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer. - Liangxiao Tang; Weixin Gai; Linqi Shi (ISCAS, 2016)

A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery. - Liangxiao Tang; Weixin Gai; Linqi Shi; Xiao Xiang (ISCAS, 2017)

A 108fsrms 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching. - Yinxuan Lyu; Jianhua Feng; Chenfeng Tu; Linqi Shi; Hongfei Ye; Weixin Gai; Dunshan Yu (ISCAS, 2018)

A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor. - Linqi Shi; Weixin Gai; Jichao Huang; Liangxiao Tang; Xiao Xiang (ISCAS, 2018)

An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor. - Linqi Shi; Weixin Gai; Xiaoting Zhi; Liangxiao Tang; Xiao Xiang (ISCAS, 2018)

A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. - Liangxiao Tang; Weixin Gai; Linqi Shi; Xiao Xiang; Kai Sheng; Ai He (ISSCC, 2018)

Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop. - Sheng Zhang; Song Jia; Hanzun Zhang; Rongshan Wei; Weixin Gai (ASICON, 2019)

Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs. - Ai He; Weixin Gai; Yufan Feng; Zhongzhu Pu; Xiao Xiang (ISCAS, 2019)

An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation. - Xiao Xiang; Weixin Gai; Linqi Shi; Ai He; Kai Sheng (ISCAS, 2019)

An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology. - Ai He; Weixin Gai; Kai Sheng; Ninghuang Li (ASICON, 2021)

A 2-Bit 4-Level 4-Wire 56Gb/s Transceiver in 14nm FinFET. - Kai Sheng; Linqi Shi; Weixin Gai; Qianting Hua; Peng Lin (ISCAS, 2021)

A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS. - Liangxiao Tang; Weixin Gai; Chih-Kong Ken Yang; Bingyi Ye; Congcong Chen (ISCAS, 2021)

A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer. - Dong Yanchi; Weixin Gai; Xiao Xiang; Haowei Niu (ISCAS, 2021)

Analog Signal Processing Circuits for a 400Gb/s 16QAM Optical Coherent Receiver. - Boyang Zhang; Weixin Gai; Haowei Niu; Bingyi Ye; Kai Sheng; Tianjian Zuo; Lei Liu (ISCAS, 2021)

56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology. - Ai He; Weixin Gai; Bingyi Ye; Boyang Zhang; Kai Sheng; Yuanliang Li (Microelectron. J., 2021)

Equal-slope baud-rate CDR algorithm with optimized eye opening. - Xiao Xiang; Weixin Gai; Ai He; Hang Zhou; Dong Yanchi (Microelectron. J., 2021)

An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC. - Cece Huang; Yuanfu Zhao; Yafei Ji; Xin Yang; Tieliang Zhang; Weixin Gai (ICTA, 2022)

A High-Linearity 14GHz 7b Phase Interpolator for Ultra-High-Speed Wireline Applications. - Ninghuang Li; Weixin Gai; Bingyi Ye; Haowei Niu; Lei Lu (ISCAS, 2022)

A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS. - Kai Sheng; Haowei Niu; Boyang Zhang; Weixin Gai; Bingyi Ye; Hang Zhou; Congcong Chen (ISSCC, 2022)

A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS. - Bingyi Ye; Kai Sheng; Weixin Gai; Haowei Niu; Boyang Zhang; Yandong He; Song Jia; Congcong Chen; Jiaqi Yu (ISSCC, 2022)

A Residue Amplifier with 85 dB DC Gain and 15 GHz Closed-Loop Bandwidth for 14-Bit 3GSPS Pipeline ADC. - Cece Huang; Weixin Gai; Yuanfu Zhao; Yafei Ji; Fei Chu; Tieliang Zhang (Circuits Syst. Signal Process., 2022)

A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS. - Kai Sheng; Weixin Gai; Zeze Feng; Haowei Niu; Bingyi Ye; Hang Zhou (ISSCC, 2023)

A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS. - Bingyi Ye; Guangdong Wu; Weixin Gai; Kai Sheng; Yandong He (ISSCC, 2023)

A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS. - Kai Sheng; Haowei Niu; Boyang Zhang; Weixin Gai; Bingyi Ye; Hang Zhou; Congcong Chen (IEEE J. Solid State Circuits, 2023)

A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS. - Bingyi Ye; Kai Sheng; Weixin Gai; Haowei Niu; Boyang Zhang; Yandong He; Song Jia; Congcong Chen; Jiaqi Yu (IEEE J. Solid State Circuits, 2023)

A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET. - Boyang Zhang; Zhifei Wang; Zeze Feng; Tianchen Ye; Bingyi Ye; Zixu Wang; Weixin Gai (VLSI Technology and Circuits, 2024)

A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS. - Bingyi Ye; Guangdong Wu; Weixin Gai; Kai Sheng; Yandong He (IEEE J. Solid State Circuits, 2024)

A 64Gb/s/wire 10.5Tb/s/mm/Layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS. - Zhifei Wang; Zhiwen Huang; Tianchen Ye; Bingyi Ye; Fangzhu Li; Wei Wang; Dunshan Yu; Weixin Gai (ISSCC, 2025)

25.5 A 99.5mW/Port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS. - Guangdong Wu; Yuanliang Li; Bingyi Ye; Fangzhu Li; Xin Liu; Haowei Niu; Ruixu Wang; Dunshan Yu; Weixin Gai (ISSCC, 2025)

A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS. - Bingyi Ye; Tianchen Ye; Tianyuan Zhong; Zhiwen Huang; Lei Shen; Boyang Zhang; Dunshan Yu; Yandong He; Weixin Gai (ISSCC, 2025)

A 50Gb/s Burst-Mode NRZ Receiver with 5-Tap FFE, 7-Tap DFE and 15ns Lock Time in 28nm CMOS for Symmetric 50G-PON. - Boyang Zhang; Tianchen Ye; Shuaizhe Ma; Tianyuan Zhong; Xin Liu; Feiyang Zhang; Bingyi Ye; Dan Li; Weixin Gai (ISSCC, 2025)

A 4×106 Gb/s Mixed-Signal PAM-4 Transceivers for Optical Direct-Detect Applications With Adaptive Linearity Compensation in 28-nm CMOS. - Boyang Zhang; Tianchen Ye; Zhifei Wang; Xin Liu; Tianyuan Zhong; Ruixu Wang; Weixin Gai (IEEE Trans. Circuits Syst. II Express Briefs, 2025)