Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. - Ramy N. Tadros; Weizhe Hua; Matheus Gibiluka; Matheus T. Moreira; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2016)

Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures. - Weizhe Hua; Ramy N. Tadros; Peter A. Beerel (ISLPED, 2016)

A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. - Ramy N. Tadros; Weizhe Hua; Matheus T. Moreira; Ney Laert Vilar Calazans; Peter A. Beerel (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Secure Information Flow Verification with Mutable Dependent Types. - Andrew Ferraiuolo; Weizhe Hua; Andrew C. Myers; G. Edward Suh (DAC, 2017)

Reverse engineering convolutional neural networks through side-channel information leaks. - Weizhe Hua; Zhiru Zhang; G. Edward Suh (DAC, 2018)

Channel Gating Neural Networks. - Weizhe Hua; Christopher De Sa; Zhiru Zhang; G. Edward Suh (CoRR, 2018)

Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating. - Weizhe Hua; Yuan Zhou; Christopher De Sa; Zhiru Zhang; G. Edward Suh (MICRO, 2019)

Channel Gating Neural Networks. - Weizhe Hua; Yuan Zhou; Christopher De Sa; Zhiru Zhang; G. Edward Suh (NeurIPS, 2019)

Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. - Yichi Zhang 006; Ritchie Zhao; Weizhe Hua; Nayun Xu; G. Edward Suh; Zhiru Zhang (ICLR, 2020)

MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration. - Weizhe Hua; Muhammad Umar 002; Zhiru Zhang; G. Edward Suh (CoRR, 2020)

GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning. - Weizhe Hua; Muhammad Umar 002; Zhiru Zhang; G. Edward Suh (CoRR, 2020)

Contrastive Weight Regularization for Large Minibatch SGD. - Qiwei Yuan; Weizhe Hua; Yi Zhou; Cunxi Yu (CoRR, 2020)

Sinan: ML-based and QoS-aware resource management for cloud microservices. - Yanqi Zhang; Weizhe Hua; Zhuangzhuang Zhou; G. Edward Suh; Christina Delimitrou (ASPLOS, 2021)

BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. - Weizhe Hua; Yichi Zhang 006; Chuan Guo 001; Zhiru Zhang; G. Edward Suh (NeurIPS, 2021)

Sinan: Data-Driven, QoS-Aware Cluster Management for Microservices. - Yanqi Zhang; Weizhe Hua; Zhuangzhuang Zhou; G. Edward Suh; Christina Delimitrou (CoRR, 2021)

Sinan: Data Driven Resource Management for Cloud Microservices. - Yanqi Zhang; Weizhe Hua; Zhuangzhuang Zhou; G. Edward Suh; Christina Delimitrou (CoRR, 2021)

GuardNN: secure accelerator architecture for privacy-preserving deep learning. - Weizhe Hua; Muhammad Umar 002; Zhiru Zhang; G. Edward Suh (DAC, 2022)

Transformer Quality in Linear Time. - Weizhe Hua; Zihang Dai; Hanxiao Liu; Quoc V. Le (ICML, 2022)

MGX: near-zero overhead memory protection for data-intensive accelerators. - Weizhe Hua; Muhammad Umar 002; Zhiru Zhang; G. Edward Suh (ISCA, 2022)

SoftVN: efficient memory protection via software-provided version numbers. - Muhammad Umar 002; Weizhe Hua; Zhiru Zhang; G. Edward Suh (ISCA, 2022)

Structured Pruning is All You Need for Pruning CNNs at Initialization. - Yaohui Cai; Weizhe Hua; Hongzheng Chen; G. Edward Suh; Christopher De Sa; Zhiru Zhang (CoRR, 2022)

Reverse-Engineering CNN Models Using Side-Channel Attacks. - Weizhe Hua; Zhiru Zhang; G. Edward Suh (IEEE Des. Test, 2022)

Information Flow Control in Machine Learning through Modular Model Architecture. - Trishita Tiwari; Suchin Gururangan; Chuan Guo 001; Weizhe Hua; Sanjay Kariyappa; Udit Gupta; Wenjie Xiong 001; Kiwan Maeng; Hsien-Hsin S. Lee; G. Edward Suh (USENIX Security Symposium, 2024)