A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power. - Fujun Bai; Baoyu Xiong; Xiaofei Xue; Weizhe Song; Baofeng Wu; Ni Fu; Bing Yu; Huifu Duan; Xiaowei Han; Alessandro Minzoni; Qiwei Ren (ASICON, 2017)