A scan disabling-based BAST scheme for test cost reduction. - Zhiqiang You; Weizheng Wang 002; Zhiping Dou; Peng Liu 045; Jishun Kuang (IEICE Electron. Express, 2011)

Switching activity reduction for scan-based BIST using weighted scan input data. - Weizheng Wang 002; Jishun Kuang; Peng Liu 045; Xin Peng; Zhiqiang You (IEICE Electron. Express, 2012)

A scan disabling-based BAST scheme for test cost and test power reduction. - Zhiqiang You; Weizheng Wang 002; Peng Liu 045; Jishun Kuang; Zheng Qin (IEICE Electron. Express, 2012)

Low power logic BIST with high test effectiveness. - Weizheng Wang 002; Peng Liu 045; Shuo Cai; Lingyun Xiang (IEICE Electron. Express, 2013)

Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm. - Peng Liu 045; Zhiqiang You; Jishun Kuang; Zhipeng Hu; Weizheng Wang 002 (IEICE Electron. Express, 2015)

A 2.7 GHz Low-Phase-Noise LC-QVCO Using the Gate-Modulated Coupling Technique. - Fei Yu 009; Qiang Tang 006; Weizheng Wang 002; Honglin Wu (Wirel. Pers. Commun., 2016)

Reliability evaluation of logic circuits based on transient faults propagation metrics. - Shuo Cai; Fei Yu 009; Weizheng Wang 002; Tieqiao Liu; Peng Liu 045; Wei Wang 229 (IEICE Electron. Express, 2017)

Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory. - Peng Liu 045; Jigang Wu; Zhiqiang You; Michael Elimu; Weizheng Wang 002; Shuo Cai (ATS, 2018)

A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks. - Weizheng Wang 002; Jincheng Wang; Wei Wang 229; Peng Liu 045; Shuo Cai (IEEE Access, 2019)

Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits. - Shuo Cai; Weizheng Wang 002; Fei Yu 009; Binyong He (J. Electron. Test., 2019)

A word-frequency-preserving steganographic method based on synonym substitution. - Lingyun Xiang; Xiao Yang; Jiahe Zhang; Weizheng Wang 002 (Int. J. Comput. Sci. Eng., 2019)

Enhancing Sensor Network Security with Improved Internal Hardware Design. - Weizheng Wang 002; Zhuo Deng; Jin Wang 001 (Sensors, 2019)

Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications. - Weizheng Wang 002; Zhuo Deng; Jin Wang 001; Arun Kumar Sangaiah; Shuo Cai; Zafer Al-Makhadmeh; Amr Tolba (Sensors, 2019)

Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults. - Shuo Cai; Binyong He; Weizheng Wang 002; Peng Liu 045; Fei Yu 009; Lairong Yin; Bo Li 051 (J. Electron. Test., 2020)

A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design. - Shuo Cai; Caicai Xie; Yan Wen; Weizheng Wang 002 (ITC-Asia, 2021)

Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory. - Peng Liu 045; Zhiqiang You; Jigang Wu; Michael Elimu; Weizheng Wang 002; Shuo Cai; Yinhe Han 001 (IEEE Trans. Emerg. Top. Comput., 2021)

An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation. - Shuo Cai; Binyong He; Sicheng Wu; Jin Wang 001; Weizheng Wang 002; Fei Yu 009 (J. Electron. Test., 2022)

Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture. - Weizheng Wang 002; Xiangqi Wang; Jin Wang 001; Neal N. Xiong; Shuo Cai; Peng Liu 045 (IEEE Trans. Syst. Man Cybern. Syst., 2022)

A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design. - Shuo Cai; Jiangbiao Ouyang; Yan Wen; Weizheng Wang 002; Fei Yu 009 (ATS, 2023)

Low-power and high-speed SRAM cells for double-node-upset recovery. - Shuo Cai; Yan Wen; Caicai Xie; Weizheng Wang 002; Fei Yu 009 (Integr., 2023)

A highly reliable and low-power cross-coupled 18T SRAM cell. - Shuo Cai; Yan Wen; Jiangbiao Ouyang; Weizheng Wang 002; Fei Yu 009; Bo Li 051 (Microelectron. J., 2023)

Four-input-C-element-based multiple-node-upset-self-recoverable latch designs. - Shuo Cai; Caicai Xie; Yan Wen; Weizheng Wang 002; Fei Yu 009; Lairong Yin (Integr., 2023)

A secure scan architecture using parallel latch-based lock. - Weizheng Wang 002; Jian Liang; Xiangqi Wang; Xianmin Pan; Shuo Cai (Integr., 2023)

A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation. - Weizheng Wang 002; Xingxing Gong; Shuo Cai; Jiamin Liu; Xiangqi Wang (IEEE Access, 2024)

A secure scan architecture using dynamic key to thwart scan-based side-channel attacks. - Weizheng Wang 002; Jinhai Chen; Xianmin Pan (Microelectron. J., 2024)

DAF: An Effective Design-for-Testability Authorization Framework Based on Obfuscation Mechanisms for Defending Complex Attacks. - Weizheng Wang 002; Xingxing Gong; Xiangqi Wang; Shuo Cai; Peng Liu 045; Neal N. Xiong (IEEE Internet Things J., 2024)

Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications. - Shuo Cai; Xinjie Liang; Zhu Huang; Weizheng Wang 002; Fei Yu 009 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

SSA: An Effective Secure Scan Architecture Based on Hidden, Randomly Inserted Keys and PUF. - Weizheng Wang 002; Zhizhi Wu; Jinhai Chen; Peng Liu 045; Shuo Cai; Neal N. Xiong (IEEE Internet Things J., 2025)