A Compact 20GHz Dynamic Latch Comparator in 65nm CMOS Process. - Jérôme Folla Kamdem; Wembe Tafo Evariste; Essimbi Zobo Bernard; Maria Liz Crespo; Andres Cicuttin (SSD, 2021)

A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage. - Jérôme Folla Kamdem; Maria Liz Crespo; Wembe Tafo Evariste; Mohammad A. S. Bhuiyan; Andres Cicuttin; Essimbi Zobo Bernard; Mamun Bin Ibne Reaz (IET Circuits Devices Syst., 2021)

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors. - Jérôme Folla Kamdem; Wembe Tafo Evariste; Essimbi Zobo Bernard; Maria Liz Crespo; Andres Cicuttin; Mamun Bin Ibne Reaz; Mohammad Arif Sobhan Bhuiyan (Sensors, 2021)

A PVT power immune compact 65 nm CMOS CSP design with a leakage current compensation feedback for CdZnTe/CdTe sensors dedicated to PET applications. - Pancha Yannick Hertz; Jérôme Folla Kamdem; Noumbissi Sidze Laure Vanessa; Wembe Tafo Evariste; Essimbi Zobo Bernard (Int. J. Circuit Theory Appl., 2022)

An Enhanced StrongArm Dynamic Latch Comparator for Low-Power and High-Speed Applications. - Noumbissi Sidze Laure Vanessa; Pancha Yannick Hertz; Wembe Tafo Evariste; Jérôme Folla Kamdem; Essimbi Zobo Bernard (J. Circuits Syst. Comput., 2025)