A Probabilistic Testability Measure for Delay Faults. - Wen Ching Wu; Chung-Len Lee (DAC, 1991)

Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. - Wen Ching Wu; Chung-Len Lee 001; Jwu E. Chen; Won Yih Lin (EDAC-ETC-EUROASIC, 1994)

Identification of robust untestable path delay faults. - Wen Ching Wu; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 1995)

Fault diagnosis of odd-even sorting networks. - Chih Wei Hu; Chung-Len Lee 001; Wen Ching Wu; Jwu E. Chen (Asian Test Symposium, 1997)

A Two-Phase Fault Simulation Scheme for Sequential Circuits. - Wen Ching Wu; Chung-Len Lee 001; Jwu E. Chen (J. Inf. Sci. Eng., 1998)

Oscillation Ring Delay Test for High Performance Microprocessors. - Wen Ching Wu; Chung-Len Lee 001; Ming Shae Wu; Jwu E. Chen; Magdy S. Abadir (J. Electron. Test., 2000)

MRAM Defect Analysis and Fault Modeli. - Chin-Lung Su; Rei-Fu Huang; Cheng-Wen Wu; Chien-Chung Hung; Ming-Jer Kao; Yeong-Jar Chang; Wen Ching Wu (ITC, 2004)

A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. - Li-Ming Denq; Rei-Fu Huang; Cheng-Wen Wu; Yeong-Jar Chang; Wen Ching Wu (MTDT, 2004)

Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle. - Ming Shae Wu; Chung-Len Lee; Yeong-Jar Chang; Wen Ching Wu (Asian Test Symposium, 2005)

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen; Ji-Jan Chen; Kun-Lun Luo; Wen Ching Wu (ITC, 2006)

Diagnosis for MRAM write disturbance fault. - Chin-Lung Su; Chih-Wea Tsai; Cheng-Wen Wu; Ji-Jan Chen; Wen Ching Wu; Chien-Chung Hung; Ming-Jer Kao (ITC, 2007)

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. - Shih-Ping Lin 001; Chung-Len Lee 001; Jwu-E Chen; Ji-Jan Chen; Kun-Lun Luo; Wen Ching Wu (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. - Pei-Wen Luo; Jwu-E Chen; Chin-Long Wey; Liang-Chia Cheng; Ji-Jan Chen; Wen Ching Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

CAD reference flow for 3D via-last integrated circuits. - Chang-Tzu Lin; Ding-Ming Kwai; Yung-Fa Chou; Ting-Sheng Chen; Wen Ching Wu (ASP-DAC, 2010)

Diagnosis of MRAM Write Disturbance Fault. - Chin-Lung Su; Chih-Wea Tsai; Ching-Yi Chen; Wan-Yu Lo; Cheng-Wen Wu; Ji-Jan Chen; Wen Ching Wu; Chien-Chung Hung; Ming-Jer Kao (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories. - Chin-Lung Su; Rei-Fu Huang; Cheng-Wen Wu; Kun-Lun Luo; Wen Ching Wu (IEEE Trans. Very Large Scale Integr. Syst., 2011)