A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology. - Wei-Zen Chen; Tai-You Lu; Yan-Ting Wang; Jhong-Ting Jian; Yi-Hung Yang; Guo-Wei Huang; Wen-De Liu; Chih-Hua Hsiao; Shu-Yu Lin; Jung Yen Liao (VLSIC, 2012)