Evaluating the abrasive wear of Zn1-xMnxO heteroepitaxial layers using a nanoscratch technique. - Yu-Ming Chang; Hua-Chiang Wen; Chu-Shou Yang; Derming Lian; Chien-Huang Tsai; Jyh-Shyang Wang; Wen-Fa Wu; Chang-Pin Chou (Microelectron. Reliab., 2010)

Evaluation of the nanoindentation behaviors of SiGe epitaxial layer on Si substrate. - Bo-Ching He; Chun-Hu Cheng; Hua-Chiang Wen; Yi-Shao Lai; Ping-Feng Yang; Meng-Hung Lin; Wen-Fa Wu; Chang-Pin Chou (Microelectron. Reliab., 2010)

Effect of annealing treatment and nanomechanical properties for multilayer Si0.8Ge0.2-Si films. - Bo-Ching He; Hua-Chiang Wen; Meng-Hung Lin; Yi-Shao Lai; Wen-Fa Wu; Chang-Pin Chou (Microelectron. Reliab., 2010)

Evaluating nanotribological behavior of annealing Si0.8Ge0.2/Si films. - Ming-Jhang Wu; Hua-Chiang Wen; Shyh-Chi Wu; Ping-Feng Yang; Yi-Shao Lai; Wen-Kuang Hsu; Wen-Fa Wu; Chang-Pin Chou (Microelectron. Reliab., 2011)

Reliability impacts of high-speed 3-bit/cell Schottky barrier nanowire charge-trapping memories. - Wei Chang; Chun-Hsing Shih; Yan-Xiang Luo; Wen-Fa Wu; Chen-Hsin Lien (Microelectron. Reliab., 2015)

Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs. - Feng-Min Lee; Po-Hao Tseng; Yu-Yu Lin; Yu-Hsuan Lin; Wei-Lun Weng; Nei-Chih Lin; Po-Jung Sung; Chien-Ting Wu; Chih-Chao Yang; Wen-Fa Wu; Chang-Hong Shen; Tuo-Hung Hou; et al. (VLSI Technology and Circuits, 2024)

3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi. - Bo-Jheng Shih; Yu-Ming Pan; Hao-Tung Chung; Chieh-Ling Lee; I-Chun Hsieh; Nein-Chih Lin; Chih-Chao Yang; Po-Tsang Huang; Hung-Ming Chen; Chiao-Yen Wang; Huan-Yu Chiu; Huang-Chung Cheng; et al. (VLSI Technology and Circuits, 2024)