A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology. - Ching-Yuan Yang; Chih-Hsiang Chang; Wen-Ger Wong (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Delta-Sigma PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology. - Ching-Yuan Yang; Chih-Hsiang Chang; Wen-Ger Wong (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)