Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing. - Ke-Ren Dai; Wen-Hao Liu 001; Yih-Lang Li (ASP-DAC, 2009)

Minimizing clock latency range in robust clock tree synthesis. - Wen-Hao Liu 001; Yih-Lang Li; Hui-Chi Chen (ASP-DAC, 2010)

Multi-threaded collision-aware global routing with bounded-length maze routing. - Wen-Hao Liu 001; Wei-Chun Kao; Yih-Lang Li; Kai-Yuan Chao (DAC, 2010)

Negotiation-based layer assignment for via count and via overflow minimization. - Wen-Hao Liu 001; Yih-Lang Li (ASP-DAC, 2011)

High-quality global routing for multiple dynamic supply voltage designs. - Wen-Hao Liu 001; Yih-Lang Li; Kai-Yuan Chao (ICCAD, 2011)

Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization. - Yen-Hung Lin; Yun-Jian Lo; Hian-Syun Tong; Wen-Hao Liu 001; Yih-Lang Li (ASP-DAC, 2012)

A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. - Wen-Hao Liu 001; Yih-Lang Li; Cheng-Kok Koh (ICCAD, 2012)

Optimizing the antenna area and separators in layer assignment of multi-layer global routing. - Wen-Hao Liu 001; Yih-Lang Li (ISPD, 2012)

NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing. - Ke-Ren Dai; Wen-Hao Liu 001; Yih-Lang Li (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Optimization of placement solutions for routability. - Wen-Hao Liu 001; Cheng-Kok Koh; Yih-Lang Li (DAC, 2013)

Routing congestion estimation with real design constraints. - Wen-Hao Liu 001; Yaoguang Wei; Cliff C. N. Sze; Charles J. Alpert; Zhuo Li 001; Yih-Lang Li; Natarajan Viswanathan (DAC, 2013)

Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. - Wen-Hao Liu 001; Cheng-Kok Koh; Yih-Lang Li (ISPD, 2013)

NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing. - Wen-Hao Liu 001; Wei-Chun Kao; Yih-Lang Li; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs. - Wen-Hao Liu 001; Min-Sheng Chang; Ting-Chi Wang (DAC, 2014)

Density-aware Detailed Placement with Instant Legalization. - Sergiy Popovych; Hung-Hao Lai; Chieh-Min Wang; Yih-Lang Li; Wen-Hao Liu 001; Ting-Chi Wang (DAC, 2014)

Metal layer planning for silicon interposers with consideration of routability and manufacturing cost. - Wen-Hao Liu 001; Tzu-Kai Chien; Ting-Chi Wang (DATE, 2014)

A study on the use of parallel wiring techniques for sub-20nm designs. - Rickard Ewetz; Wen-Hao Liu 001; Kai-Yuan Chao; Ting-Chi Wang; Cheng-Kok Koh (ACM Great Lakes Symposium on VLSI, 2014)

A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy. - Wen-Hao Liu 001; Zhen-Yu Peng; Ting-Chi Wang (ICCAD, 2014)

A study on unroutable placement recognition. - Wen-Hao Liu 001; Tzu-Kai Chien; Ting-Chi Wang (ISPD, 2014)

ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement. - Vladimir Yutsis; Ismail Bustany; David G. Chinnery; Joseph R. Shinnerl; Wen-Hao Liu 001 (ISPD, 2014)

Skillfully diminishing antenna effect in layer assignment stage. - Chih-Chien Lin; Wen-Hao Liu 001; Yih-Lang Li (VLSI-DAT, 2014)

Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition. - Wen-Hao Liu 001; Tzu-Kai Chien; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Negotiation-based track assignment considering local nets. - Man-Pan Wong; Wen-Hao Liu 001; Ting-Chi Wang (ASP-DAC, 2016)

Delay-driven layer assignment for advanced technology nodes. - Szu-Yuan Han; Wen-Hao Liu 001; Rickard Ewetz; Cheng-Kok Koh; Kai-Yuan Chao; Ting-Chi Wang (ASP-DAC, 2017)

ISPD 2018 Initial Detailed Routing Contest and Benchmarks. - Stefanus Mantik; Gracieli Posser; Wing-Kai Chow; Yixiao Ding; Wen-Hao Liu 001 (ISPD, 2018)

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. - Yibo Lin; Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; Natarajan Viswanathan; Wen-Hao Liu 001; Zhuo Li 001; Charles J. Alpert; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew. - Necati Uysal; Wen-Hao Liu 001; Rickard Ewetz (ASP-DAC, 2019)

ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. - Wen-Hao Liu 001; Stefanus Mantik; Wing-Kai Chow; Yixiao Ding; Amin Farshidi; Gracieli Posser (ISPD, 2019)

MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes. - Xinghai Zhang; Zhen Zhuang; Genggeng Liu; Xing Huang 001; Wen-Hao Liu 001; Wenzhong Guo; Ting-Chi Wang (DATE, 2020)

MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique. - Zhen Zhuang; Genggeng Liu; Xing Huang 001; Xiaotao Jia; Wen-Hao Liu 001; Wenzhong Guo (ACM Great Lakes Symposium on VLSI, 2020)

ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification. - Zhen Zhuang; Xing Huang 001; Genggeng Liu; Wenzhong Guo; Weikang Qian; Wen-Hao Liu 001 (DATE, 2021)

Challenges for Automating Package Routing. - Wen-Hao Liu 001; Bing Chen; Hua-Yu Chang; Gary Lin; Zi-Shen Lin (ISPD, 2022)

LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction. - Lieqiu Jiang; Zepeng Li; Chenpeng Bao; Genggeng Liu; Xing Huang 001; Wen-Hao Liu 001; Ting-Chi Wang (VLSI-SoC, 2022)

SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition. - Yidan Jing; Liliang Yang; Zhen Zhuang; Genggeng Liu; Xing Huang 001; Wen-Hao Liu 001; Ting-Chi Wang (VLSI-SoC, 2022)

In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence. - Andrew B. Kahng; Jian Kuang; Wen-Hao Liu 001; Bangqi Xu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars. - Genggeng Liu; Xinghai Zhang; Wenzhong Guo; Xing Huang 001; Wen-Hao Liu 001; Kai-Yuan Chao; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

GPU/ML-Enhanced Large Scale Global Routing Contest. - Rongjian Liang; Anthony Agnesina; Wen-Hao Liu 001; Haoxing Ren (ISPD, 2024)

Challenges for Automating PCB Layout. - Wen-Hao Liu 001; Anthony Agnesina; Haoxing Mark Ren (ISPD, 2024)

ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis. - Rongjian Liang; Chia-Tung Ho; Anthony Agnesina; Wen-Hao Liu 001; Haoxing Ren (MLCAD, 2024)

Paired-Spacing-Constrained Package Routing with Net Ordering Optimization. - Yi-Sian Ciou; Ying-Jie Jiang; Yi-Yu Liu; Shao-Yun Fang; Wen-Hao Liu 001 (ASP-DAC, 2025)

Invited: ISPD 2025 Performance-Driven Large Scale Global Routing Contest. - Rongjian Liang; Anthony Agnesina; Wen-Hao Liu 001; Matt Liberty; Hsin-Tzu Chang; Haoxing Ren (ISPD, 2025)

SPTA 2.0: Enhanced Scalable Parallel Track Assignment Algorithm with Two-Stage Partition Considering Timing Delay. - Huayang Cai; Pengcheng Huang; Genggeng Liu; Xing Huang 001; Yidan Jing; Wenhao Liu 001; Ting-Chi Wang (ACM Trans. Design Autom. Electr. Syst., 2025)

A Unified Deep Reinforcement Learning Approach for Constructing Rectilinear and Octilinear Steiner Minimum Tree. - Zhenkun Lin; Genggeng Liu; Xing Huang 001; Yibo Lin; Jixin Zhang; Wen-Hao Liu 001; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)