Module binding for low power clock gating. - Chun-Hua Cheng; Shih-Hsu Huang; Wen-Pin Tu (IEICE Electron. Express, 2008)

Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. - Shih-Hsu Huang; Chia-Ming Chang 002; Wen-Pin Tu; Song-Bin Pan (ASP-DAC, 2010)

Teaching three-dimensional system-in-package design automation in a semester course. - Shih-Hsu Huang; Wen-Pin Tu; Hua-Hsin Yeh; Chun-Hua Cheng (MSE, 2011)

TSV sharing through multiplexing for TSV count minimization in high-level synthesis. - Wen-Pin Tu; Yen-Hsin Lee; Shih-Hsu Huang (SoCC, 2011)

Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. - Wen-Pin Tu; Shih-Hsu Huang; Chun-Hua Cheng (ASP-DAC, 2012)

NBTI-aware dual threshold voltage assignment for leakage power reduction. - Wen-Pin Tu; Shih-Wei Wu; Shih-Hsu Huang; Mely Chen Chi (ISCAS, 2012)

High-Level Synthesis for Minimum-Area Low-Power Clock Gating. - Shih-Hsu Huang; Wen-Pin Tu; Bing-Hung Li (J. Inf. Sci. Eng., 2012)

Co-synthesis of data paths and clock control paths for minimum-period clock gating. - Wen-Pin Tu; Shih-Hsu Huang; Chun-Hua Cheng (DATE, 2013)

Low-power timing closure methodology for ultra-low voltage designs. - Wen-Pin Tu; Chung-Han Chou; Shih-Hsu Huang; Shih-Chieh Chang; Yow-Tyng Nieh; Chien-Yung Chou (ICCAD, 2013)

Low-power anti-aging zero skew clock gating. - Shih-Hsu Huang; Wen-Pin Tu; Chia-Ming Chang 002; Song-Bin Pan (ACM Trans. Design Autom. Electr. Syst., 2013)

Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew. - Tsung-Tang Lin; Wen-Pin Tu; Shih-Hsu Huang (APCCAS, 2014)

Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol. - Hua-Hsin Yeh; Wen-Pin Tu; Jian-Zhi Shen; Tung-Hua Yen; Shih-Hsu Huang (APCCAS, 2014)