A novel approach for high-level power modeling of sequential circuits using recurrent neural networks. - Wen-Tsan Hsieh; Chih-Chieh Shiue; Chien-Nan Jimmy Liu (ISCAS (4), 2005)

A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. - Wen-Tsan Hsieh; Chi-Chia Yu; Chien-Nan Jimmy Liu; Yi-Fang Chiu (PATMOS, 2006)

An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model. - Wen-Tsan Hsieh; Chi-Chia Yu; Chien-Nan Jimmy Liu; Yi-Fang Chiu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Tableless Approach for High-Level Power Modeling Using Neural Networks. - Chih-Yang Hsu; Wen-Tsan Hsieh; Chien-Nan Jimmy Liu; Jing-Yang Jou (J. Inf. Sci. Eng., 2007)

PAC duo system power estimation at ESL. - Wen-Tsan Hsieh; Jen-Chieh Yeh; Shi-Yu Huang (ASP-DAC, 2010)

System-level design exploration for 3-D stacked memory architectures. - Chi-Hung Lin; Wen-Tsan Hsieh; Hsien-Ching Hsieh; Chun-Nan Liu; Jen-Chieh Yeh (CODES+ISSS, 2011)

PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. - Chen-Wei Hsu; Jia-Lu Liao; Shan-Chien Fang; Chia-Chien Weng; Shi-Yu Huang; Wen-Tsan Hsieh; Jen-Chieh Yeh (DAC, 2011)

System power analysis with DVFS on ESL virtual platform. - Wen-Tsan Hsieh; Jen-Chieh Yeh; Shih-Che Lin; Hsing-Chuang Liu; Yi-Siou Chen (SoCC, 2011)