New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's. - Ming-Dou Ker; Wen-Yu Lo; Chung-Yu Wu (CICC, 1999)

Mew diode string design with very low leakage current for using in power supply ESD clamp circuits. - Ming-Dou Ker; Wen-Yu Lo; Hun-Hsien Chang (ISCAS, 2000)

Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process. - Ming-Dou Ker; Wen-Yu Lo (IEEE J. Solid State Circuits, 2000)

Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process. - Ming-Dou Ker; Che-Hao Chuang; Wen-Yu Lo (ICECS, 2001)

Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. - Ming-Dou Ker; Wen-Yu Lo; Tung-Yang Chen; Howard Tang; S.-S. Chen; Mu-Chun Wang (ISQED, 2001)

ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process. - Ming-Dou Ker; Chien-Hui Chuang; Kuo-Chun Hsu; Wen-Yu Lo (ISQED, 2002)

Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset IC. - Wen-Yu Lo; Ming-Dou Ker (Microelectron. Reliab., 2003)

Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels. - Ming-Dou Ker; Wei-Jen Chang; Wen-Yu Lo (ISQED, 2004)

A WebQuest-based Instruction Model for Aboriginal Students in Mathematics. - Kai-Hsiang Yang; Shan-Shan Wu; Wen-Yu Lo (ICCE, 2015)

Investigating the Effects of Mobile Learning with Cross-Age Peer Tutoring in English Learning. - Kai-Hsiang Yang; Wen-Yu Lo; Shan-Shan Wu; Wan Ling Chang (IIAI-AAI, 2015)