A Parallel Pattern Mixed-Level Fault Simulator. - Tyh-Song Hwang; Chung Len Lee 001; Wen-Zen Shen; Ching Ping Wu (DAC, 1990)

Checkpoints in irredundant two-level combinational circuits. - Jwu E. Chen; Chung-Len Lee 001; Wen-Zen Shen (J. Electron. Test., 1991)

Single-fault fault-collapsing analysis in sequential logic circuits. - Jwu E. Chen; Chung-Len Lee 001; Wen-Zen Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Coalgebraic Division for Multilevel Logic Synthesis. - Wen-Jun Hsu; Wen-Zen Shen (DAC, 1992)

SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence. - Ching Ping Wu; Chung Len Lee 001; Wen-Zen Shen (EURO-DAC, 1992)

MT-SIM a mixed-level transition fault simulator based on parallel patterns. - Chung Len Lee 001; Ching Ping Wu; Wen-Zen Shen; Tyh-Song Hwang; Shueng Dar Hwang (J. Electron. Test., 1992)

Design of Pseudoexhaustive Testable PLA with Low Overhead. - Wen-Zen Shen; Gwo-Haur Hwang; Wen-Jun Hsu; Yun-Jung Jan (IEEE Trans. Computers, 1993)

Restructuring and logic minimization for testable PLA. - Gwo-Haur Hwang; Wen-Zen Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

A cell-based power estimation in CMOS combinational circuits. - Jiing-Yuan Lin; Tai-Chien Liu; Wen-Zen Shen (ICCAD, 1994)

On the Reduction of Recorder Buffer Size for Discrete Fourier Transform Processor Design. - Wen-Zen Shen; Yi-Hsin Tao; Lan-Rong Dung (ISCAS, 1994)

Transistor reordering rules for power reduction in CMOS gates. - Wen-Zen Shen; Jiing-Yuan Lin; Fong-Wen Wang (ASP-DAC, 1995)

Fanout fault analysis for digital logic circuits. - Jwu E. Chen; Chung-Len Lee 001; Wen-Zen Shen; Beyin Chen (Asian Test Symposium, 1995)

Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. - Wen-Zen Shen; Juinn-Dar Huang; Shih-Min Chao (DAC, 1995)

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen (ICCAD, 1995)

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen (ICCAD, 1996)

A power modeling and characterization method for the CMOS standard cell library. - Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (ICCAD, 1996)

CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits. - Wen-Zen Shen; Jiing-Yuan Lin; Jyh-Ming Lu (ASP-DAC, 1997)

A power modeling and characterization method for macrocells using structure information. - Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (ICCAD, 1997)

On circuit clustering for area/delay tradeoff under capacity and pin constraints. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen; Hsien-Ho Chuang (IEEE Trans. Very Large Scale Integr. Syst., 1998)

A structure-oriented power modeling technique for macrocells. - Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A new method for constructing IP level power model based on power sensitivity. - Heng-Liang Huang; Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (ASP-DAC, 2000)

ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen (IEEE Trans. Very Large Scale Integr. Syst., 2000)

A pattern compaction technique for power estimation based on power sensitivity information. - Chih-Yang Hsu; Chaur-Wen Wei; Wen-Zen Shen (ISCAS (5), 2001)

Grouped input power sensitive transition an input sequence compaction technique for power estimation. - Heng-Liang Huang; Yeong-Ren Chen; Jing-Yang Jou; Wen-Zen Shen (ISCAS (5), 2001)