A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. - Wenbo Liu 003; Yuchun Chang; Szukang Hsien; Bo-Wei Chen; Yung-Pin Lee; Wen-Tsao Chen; Tzu-Yi Yang; Gin-Kou Ma; Yun Chiu (ISSCC, 2009)

SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration. - Pingli Huang; Szukang Hsien; Victor Lu; Peiyuan Wan; Seung-Chul Lee; Wenbo Liu 003; Bo-Wei Chen; Yung-Pin Lee; Wen-Tsao Chen; Tzu-Yi Yang; Gin-Kou Ma; Yun Chiu (CICC, 2010)

A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR. - Wenbo Liu 003; Pingli Huang; Yun Chiu (ISSCC, 2010)

Low-power high-performance SAR ADC design with digital calibration techniques - Wenbo Liu 003 (2010)

SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration. - Pingli Huang; Szukang Hsien; Victor Lu; Peiyuan Wan; Seung-Chul Lee; Wenbo Liu 003; Bo-Wei Chen; Yung-Pin Lee; Wen-Tsao Chen; Tzu-Yi Yang; Gin-Kou Ma; Yun Chiu (IEEE J. Solid State Circuits, 2011)

A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration. - Wenbo Liu 003; Pingli Huang; Yun Chiu (IEEE J. Solid State Circuits, 2011)

A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration. - Wenbo Liu 003; Pingli Huang; Yun Chiu (CICC, 2012)

Time-Interleaved Analog-to-Digital Conversion With Online Adaptive Equalization. - Wenbo Liu 003; Yun Chiu (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)