Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-high Gm, max of 559 µS/µm at VDS=1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/dec. - Kaifei Chen; Jiebin Niu; Guanhua Yang; Menggan Liu; Wendong Lu; Fuxi Liao; Kailiang Huang; Xinlv Duan; Congyan Lu; Jiawei Wang; Lingfei Wang; Mengmeng Li; et al. (VLSI Technology and Circuits, 2022)

First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s). - Menggan Liu; Zhi Li 062; Wendong Lu; Kaifei Chen; Jiebin Niu; Fuxi Liao; Zijing Wu; Congyan Lu; Weizeng Li; Di Geng; Nianduan Lu; Chunmeng Dou; et al. (VLSI Technology and Circuits, 2024)