Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang; Yin Sun; Kok-Leong Chang (ISCAS, 2011)

A comparative study on asynchronous Quasi-Delay-Insensitive templates. - Kok-Leong Chang; Tong Lin 001; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2012)

Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. - Weng-Geng Ho; Kwen-Siong Chong; Tong Lin 001; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2012)

A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. - Kok-Leong Chang; Tong Lin 001; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2013)

Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2013)

Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (APCCAS, 2014)

Synthesis of asynchronous QDI circuits using synchronous coding specifications. - Rong Zhou; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang; Weng-Geng Ho (ISCAS, 2014)

A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang; Ne Kyaw Zwa Lwin (ISIC, 2014)

High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). - Weng-Geng Ho; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2015)

Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (IET Circuits Devices Syst., 2015)

Interceptive side channel attack on AES-128 wireless communications for IoT applications. - Ali Akbar Pammu; Kwen-Siong Chong; Weng-Geng Ho; Bah-Hwee Gwee (APCCAS, 2016)

Success rate model for fully AES-128 in correlation power analysis. - Ali Akbar Pammu; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Nan Liu 002; Bah-Hwee Gwee (APCCAS, 2016)

Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications. - Nan Liu 002; Kwen-Siong Chong; Weng-Geng Ho; Bah-Hwee Gwee; Joseph Sylvester Chang (DATE, 2016)

High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. - Weng-Geng Ho; Nan Liu 002; Kyaw Zwa Lwin Ne; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2016)

Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM. - Weng-Geng Ho; Kyaw Zwa Lwin Ne; N. Prashanth Srinivas; Kwen-Siong Chong; Tony Tae-Hyoung Kim; Bah-Hwee Gwee (ISCAS, 2016)

Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack. - Weng-Geng Ho; Ali Akbar Pammu; Nan Liu 002; Kyaw Zwa Lwin Ne; Kwen-Siong Chong; Bah-Hwee Gwee (ISIC, 2016)

DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer. - James Lim; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee (ISCAS, 2017)

Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. - Kwen-Siong Chong; Weng-Geng Ho; Tong Lin 001; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation. - Weng-Geng Ho; Zixian Zheng; Kwen-Siong Chong; Bah-Hwee Gwee (DSP, 2018)

Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. - Weng-Geng Ho; Kwen-Siong Chong; Kyaw Zwa Lwin Ne; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. - Kwen-Siong Chong; Aparna Shreedhar; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Chao Wang 096; Jun Zhou 017; Bah-Hwee Gwee; Joseph S. Chang (AsianHOST, 2019)

Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications. - Weng-Geng Ho; Ali Akbar Pammu; Kyaw Zwa Lwin Ne; Kwen-Siong Chong; Bah-Hwee Gwee (SoCC, 2019)

A Secure Data-Toggling SRAM for Confidential Data Protection. - Weng-Geng Ho; Kwen-Siong Chong; Tony Tae-Hyoung Kim; Bah-Hwee Gwee (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor. - Ali Akbar Pammu; Weng-Geng Ho; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Bah-Hwee Gwee (IEEE Trans. Inf. Forensics Secur., 2019)

High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC. - Weng-Geng Ho; Chuan-Seng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Bah-Hwee Gwee (APCCAS, 2020)

A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. - Weng-Geng Ho; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Jun-Sheng Ng; Juncheng Chen; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2020)

A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES). - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee (ISCAS, 2020)

High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications. - Weng-Geng Ho; Ali Akbar Pammu; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Bah-Hwee Gwee (ISOCC, 2020)

Normalized Differential Power Analysis - for Ghost Peaks Mitigation. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Zhiping Lin 001; Joseph Sylvester Chang; Bah-Hwee Gwee (ISCAS, 2021)

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation. - Kwen-Siong Chong; Jun-Sheng Ng; Juncheng Chen; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Joseph Sylvester Chang; Bah-Hwee Gwee (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection. - Weng-Geng Ho; Kwen-Siong Chong; Tony Tae-Hyoung Kim; Bah-Hwee Gwee (IEEE Trans. Circuits Syst. II Express Briefs, 2021)