An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks. - Heng Zhang 024; Wenhe Yin; Sunan He; Yuan Du; Li Du (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 65nm 100MS/s-400MS/s Multi-Column SAR/SS ADC with Reconfigurable 2-8 Bit Resolution for Optical and In-memory Computing. - Anying Jiang; Ye Lin; Jiayuan Chen; Wenhe Yin; Yize Wang; Mingqian Yang; Li Du; Yuan Du (ISCAS, 2025)

Corrections to "An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks". - Heng Zhang 024; Wenhe Yin; Sunan He; Yuan Du; Li Du (IEEE Trans. Very Large Scale Integr. Syst., 2025)