An MOS transistor charge model for VLSI design. - Bing J. Sheu; Wen-Jay Hsu; P. K. Ko (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Digital and analog integrated-circuit design with built-in reliability. - Wen-Jay Hsu; Bing J. Sheu; Vance C. Tyree (ICCD, 1989)

An integrated-circuit reliability simulator-RELY. - Bing J. Sheu; Wen-Jay Hsu; Bang W. Lee (IEEE J. Solid State Circuits, 1989)

Testing of Analog Neural Array-Processor Chips. - Wen-Jay Hsu; Bing J. Sheu; Sudhir M. Gowda (ICCD, 1991)

Design of reliable VLSI circuits using simulation techniques. - Wen-Jay Hsu; Bing J. Sheu; Sudhir M. Gowda (IEEE J. Solid State Circuits, 1991)

Advanced integrated-circuit reliability simulation including dynamic stress effects. - Wen-Jay Hsu; Bing J. Sheu; Sudhir M. Gowda; Chang-Gyu Hwang (IEEE J. Solid State Circuits, 1992)

Testing of programmable analog neural network chips. - Sudhir M. Gowda; Bing J. Sheu; Wen-Jay Hsu (J. VLSI Signal Process., 1994)

A third-generation SPARC V9 64-b microprocessor. - Raymond A. Heald; Kathirgamar Aingaran; Chaim Amir; Michael Ang; Michael Boland; Pankaj Dixit; Gary Gouldsberry; Dale Greenley; Joel Grinberg; Jason M. Hart; Tim Horel; Wen-Jay Hsu; et al. (IEEE J. Solid State Circuits, 2000)

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor. - Hugh McIntyre; Dennis Wendell; K. James Lin; P. Kaushik; Suresh Seshadri; Alfred Wang; V. Sundararaman; Ping Wang; Song Kim; Wen-Jay Hsu; Hee-Choul Park; Gideon Levinsky; et al. (IEEE J. Solid State Circuits, 2005)

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. - Penny Li; Jinuk Luke Shin; Georgios K. Konstadinidis; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; et al. (ISSCC, 2015)

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. - Georgios K. Konstadinidis; Hongping Penny Li; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; Vijay Srinivasan; et al. (IEEE J. Solid State Circuits, 2016)