MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. - Wenji Fang; Yao Lu; Shang Liu 006; Qijun Zhang; Ceyu Xu; Lisa Wu Wills; Hongce Zhang; Zhiyao Xie (ICCAD, 2023)

WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification. - Wenji Fang; Hongce Zhang (TACAS (2), 2023)

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. - Shang Liu 006; Wenji Fang; Yao Lu; Qijun Zhang; Hongce Zhang; Zhiyao Xie (CoRR, 2023)

r-map: Relating Implementation and Specification in Hardware Refinement Checking. - Wenji Fang; Guangyu Hu; Hongce Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. - Wenji Fang; Shang Liu 006; Hongce Zhang; Zhiyao Xie (DAC, 2024)

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation. - Shang Liu 006; Yao Lu; Wenji Fang; Mengming Li; Zhiyao Xie (ICCAD, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model. - Mengming Li; Wenji Fang; Qijun Zhang; Zhiyao Xie (CoRR, 2024)

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. - Wenji Fang; Mengming Li; Min Li 019; Zhiyuan Yan 003; Shang Liu 006; Hongce Zhang; Zhiyao Xie (CoRR, 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

TTNN: A Physically Guided Deep Learning Model for Focal Depth and Epicenter Distance Estimation Based on Multistation Waveforms. - Duofa Ji; Wenji Fang; Changhai Zhai; Zelin Cao; Yuhong Ma (IEEE Trans. Geosci. Remote. Sens., 2024)

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. - Zhiyuan Yan 003; Wenji Fang; Mengming Li; Min Li 019; Shang Liu 006; Zhiyao Xie; Hongce Zhang (ASP-DAC, 2025)

A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. - Wenji Fang; Shang Liu 006; Hongce Zhang; Zhiyao Xie (ASP-DAC, 2025)

Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. - Shang Liu 006; Wenji Fang; Yao Lu; Qijun Zhang; Zhiyao Xie (ASP-DAC, 2025)

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design. - Wenji Fang; Shang Liu; Jing Wang; Zhiyao Xie (ICLR, 2025)

Profile-Guided Temporal Prefetching. - Mengming Li; Qijun Zhang; Yichuan Gao; Wenji Fang; Yao Lu; Yongqing Ren; Zhiyao Xie (ISCA, 2025)

Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. - Wenji Fang; Yao Lu; Shang Liu 006; Qijun Zhang; Ceyu Xu; Lisa Wu Wills; Hongce Zhang; Zhiyao Xie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation. - Shang Liu; Yao Lu; Wenji Fang; Mengming Li; Zhiyao Xie (CoRR, 2025)

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA. - Wenji Fang; Jing Wang; Yao Lu; Shang Liu; Yuchao Wu; Yuzhe Ma; Zhiyao Xie (CoRR, 2025)

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. - Wenji Fang; Wenkai Li; Shang Liu 006; Yao Lu; Hongce Zhang; Zhiyao Xie (CoRR, 2025)

GenEDA: Unleashing Generative Reasoning on Netlist via Multimodal Encoder-Decoder Aligned Foundation Model. - Wenji Fang; Jing Wang; Yao Lu; Shang Liu; Zhiyao Xie (CoRR, 2025)

RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. - Shang Liu 006; Wenji Fang; Yao Lu; Jing Wang 171; Qijun Zhang; Hongce Zhang; Zhiyao Xie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis. - Wenkai Li; Yao Lu; Wenji Fang; Jing Wang; Qijun Zhang; Zhiyao Xie (CoRR, 2025)