Wenjie Xiong

Orcid: 0000-0002-7626-2651

Affiliations:
  • Virginia Tech, Department of Electrical and Computer Engineering, Blacksburg, VA, USA
  • Meta AI
  • Yale University, Department of Electrical Engineering, New Haven, CT, USA (former)


According to our database1, Wenjie Xiong authored at least 42 papers between 2016 and 2024.

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Timeline

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Bibliography

2024
Designing Secure TLBs.
IEEE Des. Test, 2024

GPU-based Private Information Retrieval for On-Device Machine Learning Inference.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Survey of Approaches and Techniques for Security Verification of Computer Systems.
ACM J. Emerg. Technol. Comput. Syst., January, 2023

Abusing Commodity DRAMs in IoT Devices to Remotely Spy on Temperature.
IEEE Trans. Inf. Forensics Secur., 2023

Information Flow Control in Machine Learning through Modular Model Architecture.
CoRR, 2023

Cocktail Party Attack: Breaking Aggregation-Based Privacy in Federated Learning Using Independent Component Analysis.
Proceedings of the International Conference on Machine Learning, 2023

MACTA: A Multi-agent Reinforcement Learning Approach for Cache Timing Attacks and Detection.
Proceedings of the Eleventh International Conference on Learning Representations, 2023

MPCViT: Searching for Accurate and Efficient MPC-Friendly Vision Transformer with Heterogeneous Attention.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

SoK: Fault Injection Attacks on Cryptosystems.
Proceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy, 2023

2022
Evaluation of Cache Attacks on Arm Processors and Secure Caches.
IEEE Trans. Computers, 2022

Survey of Transient Execution Attacks and Their Mitigations.
ACM Comput. Surv., 2022

Data Leakage via Access Patterns of Sparse Features in Deep Learning-based Recommendation Systems.
CoRR, 2022

MPCViT: Searching for MPC-friendly Vision Transformer with Heterogeneous Attention.
CoRR, 2022

AutoCAT: Reinforcement Learning for Automated Exploration of Cache Timing-Channel Attacks.
CoRR, 2022

An Investigation on Data Center Cooling Systems Using FPGA-based Temperature Side Channels.
Proceedings of the 41st International Symposium on Reliable Distributed Systems, 2022

Characterization of MPC-based Private Inference for Transformer-based Models.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

2021
Leaking Information Through Cache LRU States in Commercial Processors and Secure Caches.
IEEE Trans. Computers, 2021

Understanding the Insecurity of Processor Caches Due to Cache Timing-Based Vulnerabilities.
IEEE Secur. Priv., 2021

SecNDP: Secure Near-Data Processing with Untrusted Memory.
IACR Cryptol. ePrint Arch., 2021

DRAM PUFs in Commodity Devices.
IEEE Des. Test, 2021

Cloud FPGA Cartography using PCIe Contention.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
Software Protection Using Dynamic PUFs.
IEEE Trans. Inf. Forensics Secur., 2020

Survey of Transient Execution Attacks.
CoRR, 2020

Leaking Information Through Cache LRU States.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Fingerprinting Cloud FPGA Infrastructures.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

A Benchmark Suite for Evaluating Caches' Vulnerability to Timing Attacks.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Decay-Based DRAM PUFs in Commodity Devices.
IEEE Trans. Dependable Secur. Comput., 2019

Analysis of Secure Caches Using a Three-Step Model for Timing-Based Attacks.
J. Hardw. Syst. Secur., 2019

Analysis of Secure Caches and Timing-Based Side-Channel Attacks.
IACR Cryptol. ePrint Arch., 2019

Thermal Covert Channels Leveraging Package-on-Package DRAM.
Proceedings of the 18th IEEE International Conference On Trust, 2019

SecChisel Framework for Security Verification of Secure Processor Architectures.
Proceedings of the 8th International Workshop on Hardware and Architectural Support for Security and Privacy, 2019

Secure TLBs.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Dynamic Physically Unclonable Functions.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Spying on Temperature using DRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Intrinsic Run-Time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security <sup>†</sup>.
Cryptogr., 2018

Cache timing side-channel vulnerability checking with computation tree logic.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

2017
SecChisel: Language and Tool for Practical and Scalable Security Verification of Security-Aware Hardware Architectures.
IACR Cryptol. ePrint Arch., 2017

Intrinsic Rowhammer PUFs: Leveraging the Rowhammer effect for improved security.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

2016
Practical DRAM PUFs in Commodity Devices.
IACR Cryptol. ePrint Arch., 2016

Survey of Approaches for Security Verification of Hardware/Software Systems.
IACR Cryptol. ePrint Arch., 2016

Run-Time Accessible DRAM PUFs in Commodity Devices.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2016, 2016


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