Test application time and volume compression through seed overlapping. - Wenjing Rao; Ismet Bayraktaroglu; Alex Orailoglu (DAC, 2003)

Virtual Compression through Test Vector Stitching for Scan Based Designs. - Wenjing Rao; Alex Orailoglu (DATE, 2003)

Frugal linear network-based test decompression for drastic test cost reductions. - Wenjing Rao; Alex Orailoglu; George Su (ICCAD, 2004)

Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (ITC, 2004)

Fault tolerant nanoelectronic processor architectures. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (ASP-DAC, 2005)

Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (ICCD, 2005)

Topology aware mapping of logic functions onto nanowire-based crossbar architectures. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (DAC, 2006)

Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (ETS, 2006)

Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (VTS, 2006)

Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (DATE, 2007)

Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (DSN, 2007)

Towards Nanoelectronics Processor Architectures. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (J. Electron. Test., 2007)

Towards fault tolerant parallel prefix adders in nanoelectronic systems. - Wenjing Rao; Alex Orailoglu (DATE, 2008)

Selective Hardening of NanoPLA Circuits. - Ilia Polian; Wenjing Rao (DFT, 2008)

Locality aware redundancy allocation in nanoelectronic systems. - Wenjing Rao; Alex Orailoglu; Keith Marzullo (NANOARCH, 2008)

Towards reliable nanoelectronic systems. - Wenjing Rao (2008)

Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis. - Yehua Su; Wenjing Rao (DFT, 2009)

Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures. - Yehua Su; Wenjing Rao (NANOARCH, 2009)

Logic Mapping in Crossbar-Based Nanoarchitectures. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (IEEE Des. Test Comput., 2009)

On mismatch number distribution of nanocrossbar logic mapping. - Yehua Su; Wenjing Rao (ICCD, 2010)

Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously. - Yehua Su; Wenjing Rao (ICCAD, 2011)

Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge. - Wenjing Rao; Chengmo Yang; Ramesh Karri; Alex Orailoglu (Computer, 2011)

Defect-tolerant logic hardening for crossbar-based nanosystems. - Yehua Su; Wenjing Rao (DATE, 2013)

Spare sharing network enhancement for scalable systems. - Soroush Khaleghi; Wenjing Rao (DFTS, 2013)

Constructing spare sharing networks for reliability enhancement of scalable systems. - Soroush Khaleghi; Wenjing Rao (SiPS, 2013)

Decentralized self-balancing systems. - Soumya Banerjee 004; Kai Da Zhao; Wenjing Rao; Milos Zefran (VLSI-SoC, 2013)

A standard cell approach for MagnetoElastic NML circuits. - Davide Giri; Marco Vacca; Giovanni Causapruno; Wenjing Rao; Mariagrazia Graziano; Maurizio Zamboni (NANOARCH, 2014)

An Integrated Framework Toward Defect-Tolerant Logic Implementation Onto Nanocrossbars. - Yehua Su; Wenjing Rao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

IC Piracy prevention via Design Withholding and Entanglement. - Soroush Khaleghi; Kai Da Zhao; Wenjing Rao (ASP-DAC, 2015)

On the conditions of guaranteed k-fault tolerant systems supporting on-the-fly repairs. - Soumya Banerjee 004; Wenjing Rao (ICCD, 2015)

A general approach for highly defect tolerant Parallel Prefix Adder design. - Soumya Banerjee 004; Wenjing Rao (DATE, 2016)

An STT-MRAM based strong PUF. - Soroush Khaleghi; Paolo Vinella; Soumya Banerjee 004; Wenjing Rao (NANOARCH, 2016)

A local reconfiguration based scalable fault tolerant many-processor array. - Soumya Banerjee 004; Wenjing Rao (ASP-DAC, 2017)

A General Design Framework for Sparse Parallel Prefix Adders. - Soumya Banerjee 004; Wenjing Rao (ISVLSI, 2017)

Hardware Obfuscation Using Strong PUFs. - Soroush Khaleghi; Wenjing Rao (ISVLSI, 2018)

Repairability Enhancement of Scalable Systems with Locally Shared Spares. - Soroush Khaleghi; Wenjing Rao (CoRR, 2018)

The existence of universally agreed fairest semi-matchings in any given bipartite graph. - Jian Xu; Soumya Banerjee 004; Wenjing Rao (Theor. Comput. Sci., 2020)

APUF Faults: Impact, Testing, and Diagnosis. - Yeqi Wei; Tim Fox; Vincent Dumoulin; Wenjing Rao; Natasha Devroye (DATE, 2022)

APUF Production Line Faults: Uniqueness and Testing. - Yeqi Wei; Wenjing Rao; Natasha Devroye (DATE, 2023)

Active learning for fast and slow modeling attacks on Arbiter PUFs. - Vincent Dumoulin; Wenjing Rao; Natasha Devroye (DSD, 2023)

A scientific paper recommendation method using the time decay heterogeneous graph. - Zhenye Huang; Deyou Tang; Rong Zhao; Wenjing Rao (Scientometrics, 2024)

On the Response Entropy of APUFs. - Vincent Dumoulin; Wenjing Rao; Natasha Devroye (J. Hardw. Syst. Secur., 2024)

Challenge Selection for Salvaging Faulty APUFs. - Yeqi Wei; Wenjing Rao; Natasha Devroye (VTS, 2025)