Exact Timing Analysis for Asynchronous Systems. - Wenmian Hua; Rajit Manohar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Cyclone: A Static Timing and Power Engine for Asynchronous Circuits. - Wenmian Hua; Yi-Shan Lu; Keshav Pingali; Rajit Manohar (ASYNC, 2020)

An Open-Source EDA Flow for Asynchronous Logic. - Samira Ataei; Wenmian Hua; Yihang Yang; Rajit Manohar; Yi-Shan Lu; Jiayuan He 003; Sepideh Maleki; Keshav Pingali (IEEE Des. Test, 2021)