Optimal Position of Isolator to Suppress Double Rayleigh Backscattering Noise in Fiber Raman Amplifiers. - Wenning Jiang; Jianping Chen; Junhe Zhou (IEICE Trans. Electron., 2005)

A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. - Wenning Jiang; Yan Zhu 001; Chi-Hang Chan; Boris Murmann; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2018)

A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier. - Wenning Jiang; Yan Zhu 001; Minglei Zhang; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2019)

A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier. - Wenning Jiang; Yan Zhu 001; Minglei Zhang; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler. - Wenning Jiang; Yan Zhu 001; Chi-Hang Chan; Boris Murmann; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. - Danfeng Zhai; Wenning Jiang; Xinru Jia; Jingchao Lan; Mingqiang Guo; Sai-Weng Sin; Fan Ye 001; Qi Liu 010; Junyan Ren; Chixiao Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. - Jie Liao; Bo Jiao; Jinshan Zhang 006; Shiwei Liu 002; Hao Jiang 024; Jun Tao 001; Wenning Jiang; Qi Liu 010; Lihua Zhang; Haozhe Zhu; Chixiao Chen (ISCAS, 2023)

A Modified Two-Stage Cascaded Hybrid Converter with Reduced Conduction Loss, Self-Balanced Flying Capacitors and Simplified Interleaving PWM. - Chuang Wang 004; Wenning Jiang (ISCAS, 2023)

A Modified Interleaving Resonant Switched Capacitor Converter with Reduced Output Resistance and In-Situ Startup. - Chuang Wang 004; Wenning Jiang (ISCAS, 2023)

A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue Amplifier. - Xinsheng Wang; Maosong Shi; Peizhe Li; Jianwei Liu; Zhangcheng Huang 001; Chixiao Chen; Wenning Jiang (ISCAS, 2023)

A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. - Shiwei Liu 002; Peizhe Li; Jinshan Zhang 006; Yunzhengmao Wang; Haozhe Zhu; Wenning Jiang; Shan Tang; Chixiao Chen; Qi Liu 010; Ming Liu 022 (ISSCC, 2023)

A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. - Wenning Jiang; Yan Zhu 001; Chixiao Chen; Hao Xu 005; Qi Liu 010; Ming Liu 022; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2023)

A Novel Stimulus Artifact Suppression System Using An Impedance-based Template. - Yirui Liu; Weiqiang Zhang; Wenning Jiang; Xiao Liu (BioCAS, 2024)

A TDM-based Analog Front-End for Ear-EEG Recording with 74.5-G Ω Input Impedance, 384-mV DC Tolerance and 0.27-μ Vrms Input-Referred Noise. - Huiyong Zheng; Wenning Jiang; Xiao Liu (BioCAS, 2024)

A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration. - Wenning Jiang; Yunbin Luo; Peizhe Li; Ji Guo; Chixiao Chen; Qi Liu 010 (CICC, 2024)

EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration. - Handa Sun; Zhaori Bi; Wenning Jiang; Ye Lu 005; Changhao Yan; Fan Yang 001; Wenchuang Hu; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (DAC, 2024)