A 65 nm uneven-dual-core SoC based platform for multi-device collaborative computing. - Wenping Zhu; Leibo Liu; Shouyi Yin; Yuan Dong; Shaojun Wei; Eugene Y. Tang; Jiqiang Song; Jinzhan Peng (ISCAS, 2014)

An uneven-dual-core processor based mobile platform for facilitating the collaboration among various embedded electronic devices. - Leibo Liu; Wenping Zhu; Shouyi Yin; Eugene Tang; Paul Peng (IEEE Trans. Consumer Electron., 2014)

A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction. - Guangli Jiang; Leibo Liu; Wenping Zhu; Shouyi Yin; Shaojun Wei (DAC, 2015)

A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction. - Guangli Jiang; Leibo Liu; Wenping Zhu; Shouyi Yin; Shaojun Wei (Sensors, 2015)

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator. - Wenping Zhu; Leibo Liu; Guangli Jiang; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. Video Technol., 2016)

A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment. - Qiang Wang; Leibo Liu; Wenping Zhu; Huiyu Mo; Chenchen Deng; Shaojun Wei (DAC, 2017)

L-MPC: A LUT based Multi-Level Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network. - Hong Liu; Leibo Liu; Wenping Zhu; Qiang Li 052; Huiyu Mo; Shaojun Wei (DAC, 2019)

A 1.17 TOPS/W, 150fps Accelerator for Multi-Face Detection and Alignment. - Huiyu Mo; Leibo Liu; Wenping Zhu; Qiang Li 052; Hong Liu; Wenjing Hu; Yao Wang; Shaojun Wei (DAC, 2019)

A Novel Wavelet Denoising Pre-processing Algorithm for TDOA Localization. - Wenping Zhu; Shujuan Hou; Yuan Yuan (ICCC, 2019)

A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution. - Leibo Liu; Wenping Zhu; Shouyi Yin; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching. - Leibo Liu; Qiang Wang; Wenping Zhu; Huiyu Mo; Tianchen Wang; Shouyi Yin; Yiyu Shi 001; Shaojun Wei (IEEE Trans. Circuits Syst. Video Technol., 2019)

Face Alignment With Expression- and Pose-Based Adaptive Initialization. - Huiyu Mo; Leibo Liu; Wenping Zhu; Shouyi Yin; Shaojun Wei (IEEE Trans. Multim., 2019)

TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks. - Huiyu Mo; Leibo Liu; Wenjing Hu; Wenping Zhu; Qiang Li 052; Ang Li; Shouyi Yin; Jian Chen; Xiaowei Jiang; Shaojun Wei (MICRO, 2020)

Deterministic conversion rule for CNNs to efficient spiking convolutional neural networks. - Xu Yang 017; Zhongxing Zhang; Wenping Zhu; Shuangming Yu; Liyuan Liu; Nanjian Wu (Sci. China Inf. Sci., 2020)

A High-performance Hardware Implementation of Saber Based on Karatsuba Algorithm. - Yihong Zhu; Min Zhu 001; Bohan Yang 001; Wenping Zhu; Chenchen Deng; Chen Chen 083; Shaojun Wei; Leibo Liu (IACR Cryptol. ePrint Arch., 2020)

A Multi-Task Hardwired Accelerator for Face Detection and Alignment. - Huiyu Mo; Leibo Liu; Wenping Zhu; Qiang Li 052; Hong Liu; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. Video Technol., 2020)

9.2A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction. - Huiyu Mo; Wenping Zhu; Wenjing Hu; Guangbin Wang; Qiang Li 052; Ang Li; Shouyi Yin; Shaojun Wei; Leibo Liu (ISSCC, 2021)

LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR. - Yihong Zhu; Min Zhu 001; Bohan Yang 001; Wenping Zhu; Chenchen Deng; Chen Chen 083; Shaojun Wei; Leibo Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 460 GOPS/W Improved Mnemonic Descent Method-Based Hardwired Accelerator for Face Alignment. - Huiyu Mo; Leibo Liu; Wenping Zhu; Qiang Li 052; Shouyi Yin; Shaojun Wei (IEEE Trans. Multim., 2021)

A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems. - Yihong Zhu; Wenping Zhu; Min Zhu 001; Chongyang Li; Chenchen Deng; Chen Chen 083; Shuying Yin; Shouyi Yin; Shaojun Wei; Leibo Liu (ISSCC, 2022)

Compact GF(2) systemizer and optimized constant-time hardware sorters for Key Generation in Classic McEliece. - Yihong Zhu; Wenping Zhu; Chen Chen 083; Min Zhu 001; Zhengdong Li; Shaojun Wei; Leibo Liu (IACR Cryptol. ePrint Arch., 2022)

A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction. - Huiyu Mo; Wenping Zhu; Wenjing Hu; Qiang Li 052; Ang Li; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE J. Solid State Circuits, 2022)

BitCluster: Fine-Grained Weight Quantization for Load-Balanced Bit-Serial Neural Network Accelerators. - Ang Li; Huiyu Mo; Wenping Zhu; Qiang Li 052; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium. - Cankun Zhao; Neng Zhang 002; Hanning Wang; Bohan Yang 001; Wenping Zhu; Zhengdong Li; Min Zhu 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

Mckeycutter: A High-throughput Key Generator of Classic McEliece on Hardware. - Yihong Zhu; Wenping Zhu; Chen Chen 083; Min Zhu 001; Zhengdong Li; Shaojun Wei; Leibo Liu (DAC, 2023)

RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems. - Yihong Zhu; Wenping Zhu; Chongyang Li; Min Zhu 001; Chenchen Deng; Chen Chen 083; Shuying Yin; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE J. Solid State Circuits, 2023)

Sparse Polynomial Multiplication-Based High-Performance Hardware Implementation for CRYSTALS-Dilithium. - Hang Zhao; Cankun Zhao; Wenping Zhu; Bohan Yang 001; Shaojun Wei; Leibo Liu (HOST, 2024)

16.2 A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems. - Yihong Zhu; Wenping Zhu; Yi Ouyang; Junwen Sun; Min Zhu 001; Qi Zhao; Jinjiang Yang; Chen Chen 083; Qichao Tao; Guang Yang; Aoyang Zhang; Shaojun Wei; et al. (ISSCC, 2024)

Breaking Ground: A New Area Record for Low-Latency First-Order Masked SHA-3 Advancing from the 4x Area Era to the 3x Area Era. - Cankun Zhao; Hang Zhao; Jiangxue Liu; Bohan Yang 001; Wenping Zhu; Shuying Yin; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform. - Yi Huang; Xinsheng Gong; Xiangyu Kong; Dibei Chen; Jianfeng Zhu 001; Wenping Zhu; Liangwei Li; Mingyu Gao 001; Shaojun Wei; Aoyang Zhang; Leibo Liu (HPCA, 2025)

17.2 A 28nm 4.05µJ/Encryption 8.72kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Client-Server Computing. - Sijia Lu; Wenping Zhu; Bohan Yang 001; Jiajun Yang; Tongwei Dai; Chen Chen 083; Xiangdong Han; Jinjiang Yang; Hanning Wang; Min Zhu 001; Shaojun Wei; Aoyang Zhang; et al. (ISSCC, 2025)

A High-performance NTT/MSM Accelerator for Zero-knowledge Proof Using Load-balanced Fully-pipelined Montgomery Multiplier. - Xiangren Chen; Bohan Yang 001; Wenping Zhu; Hanning Wang; Qichao Tao; Shuying Yin; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

On the Characterization of Phase Noise for the Robust and Resilient PLL-TRNG Design. - Ziheng Ma; Bohan Yang 001; Wenping Zhu; Hanning Wang; Yi Ouyang; Min Zhu 001; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

FalconSign: An Efficient and High-Throughput Hardware Architecture for Falcon Signature Generation. - Yi Ouyang; Yihong Zhu; Wenping Zhu; Bohan Yang 001; Zirui Zhang; Hanning Wang; Qichao Tao; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

PQPU: A 4.4-μJ/Op 69.4-kOPS Agile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems. - Yihong Zhu; Wenping Zhu; Yi Ouyang; Junwen Sun; Qi Zhao; Min Zhu 001; Jinjiang Yang; Chen Chen 083; Qichao Tao; Hanning Wang; Guang Yang; Shaojun Wei; et al. (IEEE J. Solid State Circuits, 2025)