Latency Minimal Scheduling with Maximum Instruction Parallelism. - Zhenghua Gu; Wenqin Wan; Chang Wu (ASICON, 2019)

Dependency Graph-based High-level Synthesis for Maximum Instruction Parallelism. - Zhenghua Gu; Wenqin Wan; Jundong Xie; Chang Wu (ACM Trans. Reconfigurable Technol. Syst., 2021)