A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. - Bonan Yan; Jeng-Long Hsu; Pang-Cheng Yu; Chia-Chi Lee; Yaojun Zhang; Wenshuo Yue; Guoqiang Mei; Yuchao Yang 001; Yue Yang; Hai Li 001; Yiran Chen 001; Ru Huang 001 (ISSCC, 2022)

Grasp Compliant Control Using Adaptive Admittance Control Methods for Flexible Objects. - Qirong Tang; Hao Yang; Wenrui Wang; Min Yu; Lou Zhong; Baoping Ma; Wenshuo Yue (ICIRA (1), 2023)

Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling. - Yihan Fu; Daijing Shi; Anjunyi Fan; Wenshuo Yue; Yuchao Yang 001; Ru Huang 001; Bonan Yan (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

PEARL: FPGA-Based Reinforcement Learning Acceleration with Pipelined Parallel Environments. - Jiayi Li; Hongxiao Zhao; Wenshuo Yue; Yihan Fu; Daijing Shi; Anjunyi Fan; Yuchao Yang; Bonan Yan (DATE, 2025)

PROCA: Programmable Probabilistic Processing Unit Architecture with Accept/Reject Prediction & Multicore Pipelining for Causal Inference. - Yihan Fu; Anjunyi Fan; Wenshuo Yue; Hongxiao Zhao; Daijing Shi; Qiuping Wu; Jiayi Li; Xiangyu Zhang; Yaoyu Tao; Yuchao Yang 001; Bonan Yan (HPCA, 2025)