Speculative Thread Execution in a Multithreaded Dataflow Architecture. - Wentong Li 003; Krishna M. Kavi; Afrin Naz; Philip H. Sweany (PDCS, 2006)

A Hardware Assisted High Performance PHK Memory Manager. - Wentong Li 003; Saraju P. Mohanty; Krishna M. Kavi (PDCS, 2006)

A Study of Reconfigurable Split Data Caches and Instruction Caches. - Afrin Naz; Krishna M. Kavi; Philip H. Sweany; Wentong Li 003 (PDCS, 2006)

A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator. - Wentong Li 003; Saraju P. Mohanty; Krishna M. Kavi (IEEE Comput. Archit. Lett., 2006)

Tiny split data-caches make big performance impact for embedded applications. - Afrin Naz; Krishna M. Kavi; Wentong Li 003; Philip H. Sweany (J. Embed. Comput., 2006)

Making a case for split data caches for embedded applications. - Afrin Naz; Krishna M. Kavi; Mehran Rezaei; Wentong Li 003 (SIGARCH Comput. Archit. News, 2006)

Feasibility of decoupling memory management from the execution pipeline. - Wentong Li 003; Mehran Rezaei; Krishna M. Kavi; Afrin Naz; Philip H. Sweany (J. Syst. Archit., 2007)

A Non-blocking Multithreaded Architecture with Support for Speculative Threads. - Krishna M. Kavi; Wentong Li 003; Ali R. Hurson (ICA3PP, 2008)