Backtracking Based Handoff Rerouting Algorithm for WiMAX Mesh Mode. - Wenfeng Du; Weijia Jia 001; Wenyan Lu (UIC, 2006)

A Base Station-Coordinated Contention Resolution for IEEE 802.16 PMP Networks. - Wenyan Lu; Weijia Jia 001; Wenfeng Du; Lidong Lin (UIC, 2006)

Centralized Scheduling and Channel Assignment in Multi-Channel Single-Transceiver WiMax Mesh Network. - Peng Du; Weijia Jia 001; Liusheng Huang; Wenyan Lu (WCNC, 2007)

Performance Analysis of IEEE 802.16 Multicast and Broadcast Polling based Bandwidth Request. - Lidong Lin; Weijia Jia 001; Wenyan Lu (WCNC, 2007)

Analysis of channel allocation scheme for wireless cellular networks. - Wenfeng Du; Weijia Jia 001; Guojun Wang 001; Wenyan Lu (Int. J. Ad Hoc Ubiquitous Comput., 2009)

Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators. - Weina Lu; Wenyan Lu; Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (FPL, 2017)

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks. - Wenyan Lu; Guihai Yan; Jiajun Li; Shijun Gong; Yinhe Han 001; Xiaowei Li 001 (HPCA, 2017)

Exploiting the Potential of Computation Reuse Through Approximate Computing. - Xin He; Shuhao Jiang; Wenyan Lu; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Multi Scale Comput. Syst., 2017)

CCR: A concise convolution rule for sparse neural network accelerators. - Jiajun Li; Guihai Yan; Wenyan Lu; Shuhao Jiang; Shijun Gong; Jingya Wu; Xiaowei Li 001 (DATE, 2018)

SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators. - Jiajun Li; Guihai Yan; Wenyan Lu; Shuhao Jiang; Shijun Gong; Jingya Wu; Xiaowei Li 001 (DATE, 2018)

AxTrain: Hardware-Oriented Neural Network Training for Approximate Inference. - Xin He; Liu Ke 001; Wenyan Lu; Guihai Yan; Xuan Zhang 001 (ISLPED, 2018)

Joint Design of Training and Hardware Towards Efficient and Accuracy-Scalable Neural Network Inference. - Xin He; Wenyan Lu; Guihai Yan; Xuan Zhang 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

AdaFlow: Aggressive Convolutional Neural Networks Approximation by Leveraging the Input Variability. - Wenyan Lu; Guihai Yan; Xiaowei Li 001 (J. Low Power Electron., 2018)

TNPU: an efficient accelerator architecture for training convolutional neural networks. - Jiajun Li; Guihai Yan; Wenyan Lu; Shuhao Jiang; Shijun Gong; Jingya Wu; Junchao Yan; Xiaowei Li 001 (ASP-DAC, 2019)

ShuntFlow: An Efficient and Scalable Dataflow Accelerator Architecture for Streaming Applications. - Shijun Gong; Jiajun Li; Wenyan Lu; Guihai Yan; Xiaowei Li 001 (DAC, 2019)

MLA: Machine Learning Adaptation for Realtime Streaming Financial Applications. - Jingya Wu; Wenyan Lu; Guihai Yan; Xiaowei Li 001 (IGSC, 2019)

Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks. - Wenyan Lu; Guihai Yan; Jiajun Li; Shijun Gong; Shuhao Jiang; Jingya Wu; Xiaowei Li 001 (IEEE Trans. Computers, 2019)

SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks. - Jiajun Li; Guihai Yan; Wenyan Lu; Shijun Gong; Shuhao Jiang; Jingya Wu; Xiaowei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2019)

A Quantitative Exploration of Collaborative Pruning and Approximation Computing Towards Energy Efficient Neural Networks. - Xin He; Guihai Yan; Wenyan Lu; Xuan Zhang 001; Liu Ke 001 (IEEE Des. Test, 2020)

ShuntFlowPlus: An Efficient and Scalable Dataflow Accelerator Architecture for Stream Applications. - Shijun Gong; Jiajun Li; Wenyan Lu; Guihai Yan; Xiaowei Li 001 (ACM J. Emerg. Technol. Comput. Syst., 2021)

DOE: Database Offloading Engine for Accelerating SQL Processing. - Wenyan Lu; Yan Chen; Jingya Wu; Yu Zhang 027; Xiaowei Li 001; Guihai Yan (ICDE Workshops, 2022)

Portrait: A holistic computation and bandwidth balanced performance evaluation model for heterogeneous systems. - Jingya Wu; Wenyan Lu; Guihai Yan; Xiaowei Li 001 (Sustain. Comput. Informatics Syst., 2022)

Co-ViSu: a Video Super-Resolution Accelerator Exploiting Codec Information Reuse. - Haishuang Fan; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (FPL, 2023)

M2VT: A Multi-Output Encoder Accelerator for Multiple-Way Video Transcoding. - Haishuang Fan; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (ACM Great Lakes Symposium on VLSI, 2023)

KPU-SQL: Kernel Processing Unit for High-Performance SQL Acceleration. - Hao Kong; Haishuang Fan; Jingya Wu; Liyun Cheng; Yan Chen; Wenyan Lu; Guihai Yan; Xiaowei Li 001 (ACM Great Lakes Symposium on VLSI, 2023)

Optimize the TX Architecture of RDMA NIC for Performance Isolation in the Cloud Environment. - Yunkun Liao; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (ACM Great Lakes Symposium on VLSI, 2023)

Exploring the Empowerment of Chinese Women's Discourse in Tik Tok. - Qian Wu; Hang Jiang; Wenyan Lu (HCI (12), 2023)

BitColor: Accelerating Large-Scale Graph Coloring on FPGA with Parallel Bit-Wise Engines. - Haishuang Fan; Ming Li; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (ICPP, 2023)

FlatProxy: A DPU-centric Service Mesh Architecture for Hyperscale Cloud-native Application. - Ming Li; Wenyan Lu; Hanyue Lin; Jingya Wu; Yu Zhang 027; Guihai Yan (CoRR, 2023)

DOE: database offloading engine for accelerating SQL processing. - Hao Kong; Wenyan Lu; Yan Chen; Jingya Wu; Yu Zhang 027; Guihai Yan; Xiaowei Li 001 (Distributed Parallel Databases, 2023)

TianMen: a DPU-based storage network offloading structure for disaggregated datacenters. - Weiyue Zhao; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (SoCC, 2024)

Co-Via: A Video Frame Interpolation Accelerator Exploiting Codec Information Reuse. - Haishuang Fan; Qichu Sun; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (DAC, 2024)

PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency. - Yunkun Liao; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (DAC, 2024)

Athena: Add More Intelligence to RMT-Based Network Data Plane with Low-Bit Quantization. - Yunkun Liao; Hanyue Lin; Jingya Wu; Wenyan Lu; Huawei Li 001; Xiaowei Li 001; Guihai Yan (Euro-Par (2), 2024)

Efficient RNIC Cache Side-Channel Attack Detection Through DPU-Driven Architecture. - Yunkun Liao; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (Euro-Par (2), 2024)

AMST: Accelerating Large-Scale Graph Minimum Spanning Tree Computation on FPGA. - Haishuang Fan; Rui Meng; Qichu Sun; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (IPDPS, 2024)

DPU-Direct: Unleashing Remote Accelerators via Enhanced RDMA for Disaggregated Datacenters. - Yunkun Liao; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (IEEE Trans. Computers, 2024)

FUS: FPGA-based Universal Sketch with homogeneous and heterogeneous memory architectures. - Yunkun Liao; Jingya Wu; Wenyan Lu; Huawei Li 001; Xiaowei Li 001; Guihai Yan (CCF Trans. High Perform. Comput., 2025)

KPU: Kernel Processing Unit for in-Memory Analytical Query Processing. - Jingya Wu; Wenyan Lu; Haishuang Fan; Hao Kong; Xiaowei Li 001; Guihai Yan (IEEE Trans. Computers, 2025)