Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications. - Stefaan Note; Werner Geurts; Francky Catthoor; Hugo De Man (DAC, 1991)

Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications. - Werner Geurts; Stefaan Note; Francky Catthoor; Hugo De Man (VLSI, 1991)

Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing. - Werner Geurts; Francky Catthoor; Hugo De Man (DAC, 1992)

Testability analysis in high level data path synthesis. - Johannes Steensma; Werner Geurts; Francky Catthoor; Hugo De Man (J. Electron. Test., 1993)

Loop transformation methodology for fixed-rate video, image and telecom processing applications. - Francky Catthoor; Werner Geurts; Hugo De Man (ASAP, 1994)

Chess: retargetable code generation for embedded DSP processors. - Dirk Lanneer; Johan Van Praet; Augusli Kifli; Koen Schoofs; Werner Geurts; Filip Thoen; Gert Goossens (Code Generation for Embedded Processors, 1994)

Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization. - Francis Depuydt; Werner Geurts; Gert Goossens; Hugo De Man (EDAC-ETC-EUROASIC, 1994)

Quadratic zero-one programming-based synthesis of application-specific data paths. - Werner Geurts; Francky Catthoor; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A Graph Based Processor Model for Retargetable Code Generation. - Johan Van Praet; Dirk Lanneer; Gert Goossens; Werner Geurts; Hugo De Man (ED&TC, 1996)

Embedded software in real-time signal processing systems: design technologies. - Gert Goossens; Johan Van Praet; Dirk Lanneer; Werner Geurts; Augusli Kifli; Clifford Liem; Pierre G. Paulin (Proc. IEEE, 1997)

Solving large scale assignment problems in high-level synthesis by approximative quadratic programming. - Florin Balasa; Werner Geurts; Francky Catthoor; Hugo De Man (ACM Great Lakes Symposium on VLSI, 2001)

Processor modeling and code selection for retargetable compilation. - Johan Van Praet; Dirk Lanneer; Werner Geurts; Gert Goossens (ACM Trans. Design Autom. Electr. Syst., 2001)

Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite. - Gert Goossens; Dirk Lanneer; Werner Geurts; Johan Van Praet (SoC, 2006)

A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report. - Roberto Ammendola; Andrea Biagioni; Ottorino Frezza; Werner Geurts; Gert Goossens; Francesca Lo Cicero; Alessandro Lonardo; Pier Stanislao Paolucci; Davide Rossetti; Francesco Simula; Laura Tosoratto; Piero Vicini (CoRR, 2013)

ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces. - Roberto Ammendola; Andrea Biagioni; Ottorino Frezza; Werner Geurts; Gert Goossens; Francesca Lo Cicero; Alessandro Lonardo; Pier Stanislao Paolucci; Davide Rossetti; Francesco Simula; Laura Tosoratto; Piero Vicini (Future Gener. Comput. Syst., 2015)