A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators. - Westerley Carvalho; Michael Canesche; Lucas Reis; Frank Sill Torres; Lucas B. da Silva; Peter Jamieson; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (FPT, 2020)

An Open Source Custom K-means Generator for AWS Cloud FPGA Accelerators. - Lucas Bragança; Michael Canesche; Jeronimo Costa Penha; Westerley Carvalho; Giovanni Comarela; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (SBESC, 2021)

TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs. - Michael Canesche; Marcelo M. Menezes; Westerley Carvalho; Frank Sill Torres; Peter Jamieson; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

You Only Traverse Twice: A YOTT Placement, Routing, and Timing Approach for CGRAs. - Michael Canesche; Westerley Carvalho; Lucas Reis; Matheus Aguilar de Oliveira; Salles V. G. Magalhães; Peter Jamieson; José Augusto Miranda Nacif; Ricardo Ferreira 001 (ACM Trans. Embed. Comput. Syst., 2021)

Heterogeneous reconfigurable architectures for machine learning dataflows. - Westerley Carvalho; Michael Canesche; Lucas Reis; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (Concurr. Comput. Pract. Exp., 2023)