A built-in test circuit for open defects at interconnects between dies in 3D ICs. - Widianto; Hiroyuki Yotsuyanagi; Akira Ono; Masao Takagi; Masaki Hashizume (3DIC, 2011)

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs. - Widianto; Masaki Hashizume; Shohei Suenaga; Hiroyuki Yotsuyanagi; Akira Ono; Shyue-Kung Lu; Zvi Roth (IEICE Trans. Inf. Syst., 2016)