A review of fault-tolerant techniques for the enhancement of integrated circuit yield. - Will R. Moore (Proc. IEEE, 1986)

Parallel architectures for AI semantic network processing. - José G. Delgado-Frias; Will R. Moore (Knowl. Based Syst., 1988)

Imperfectly connected 2D arrays for image processing. - John A. Trotter; Will R. Moore (FTCS, 1989)

A semantic network architecture for artificial intelligence processing. - José G. Delgado-Frias; Will R. Moore (TAI, 1989)

Vlsi Devices and Circuits for Neural Networks. - Howard C. Card; Will R. Moore (Int. J. Neural Syst., 1989)

Testing a motion estimator array. - William P. Marnane; Will R. Moore (ASAP, 1990)

Silicon models of associative learning in Aplysia. - Howard C. Card; Will R. Moore (Neural Networks, 1990)

Multiple Fault Diagnosis in Printed Circuit Boards. - S. J. Barnfield; Will R. Moore (ITC, 1993)

Testing VLSI regular arrays. - William P. Marnane; Will R. Moore (J. Electron. Test., 1995)

Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm. - Ovidio V. Maiuri; Will R. Moore (VTS, 1998)

Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything? - Will R. Moore; Guido Gronthoud; Keith Baker; Maurice Lousberg (ITC, 2000)

Stuck-open fault diagnosis with stuck-at model. - Xinyue Fan; Will R. Moore; Camelia Hora; Guido Gronthoud (ETS, 2005)

A novel stuck-at based method for transistor stuck-open fault diagnosis. - Xinyue Fan; Will R. Moore; Camelia Hora; Guido Gronthoud (ITC, 2005)

A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis. - Xinyue Fan; Will R. Moore; Camelia Hora; Mario Konijnenburg; Guido Gronthoud (VTS, 2006)

Extending gate-level diagnosis tools to CMOS intra-gate faults. - Xinyue Fan; Will R. Moore; Camelia Hora; Guido Gronthoud (IET Comput. Digit. Tech., 2007)