High level hierarchical fault simulation techniques. - William A. Rogers; Jacob A. Abraham (ACM Conference on Computer Science, 1985)

CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator. - William A. Rogers; Jacob A. Abraham (ITC, 1985)

Structured Functional Level Test Generation Using Binary Decision Diagrams. - Hongtao P. Chang; William A. Rogers; Jacob A. Abraham (ITC, 1986)

Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations. - William A. Rogers; John F. Guzolek; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Fault Simulation in a Distributed Environment. - Patrick A. Duba; Rabindra K. Roy; Jacob A. Abraham; William A. Rogers (DAC, 1988)

The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms - William A. Rogers (1988)

FANHAT: fanout oriented hierarchical automatic test generation system. - Hyoung B. Min; William A. Rogers; Hwei-Tsu Ann Luh (ICCAD, 1989)

Search Strategy Switching: An Alternative to Increased Backtracking. - Hyoung B. Min; William A. Rogers (ITC, 1989)

Generating Single-Stuck-Fault Coverage from a Collapsed-Fault Set. - Mark A. Heap; William A. Rogers (Computer, 1989)

Search strategy switching: A cost model and an analysis of backtracking. - Hyoung B. Min; William A. Rogers (J. Electron. Test., 1990)

The Impedance Fault Model and Design for Robust Impedance Fault Testability. - Mark D. Sloan; William A. Rogers; Srihari Shoroff (ICCAD, 1991)

STarS: a target switching algorithm for sequential test generation. - Mark A. Heap; William A. Rogers; William B. Burns (VTS, 1991)

A Synthesis Algorithm for Two-Level XOR Based Circuits. - Mark A. Heap; William A. Rogers; M. Ray Mercer (ICCD, 1992)

A test methodology for finite state machines using partial scan design. - Hyoung B. Min; William A. Rogers (J. Electron. Test., 1992)

Hierarchical test pattern generation: a cost model and implementation. - Hyoung B. Min; Hwei-Tsu Ann Luh; William A. Rogers (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits. - Sanghyeon Baeg; William A. Rogers (ICCD, 1994)

Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation. - Sanghyeon Baeg; William A. Rogers (ITC, 1994)

A cost-effective design for testability: clock line control and test generation using selective clocking. - Sanghyeon Baeg; William A. Rogers (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)