A signal integrity-based link performance simulation platform. - Yuming Tao; William Bereza; Rakesh H. Patel; Sergey Y. Shumarayev; Tad A. Kwasniewski (CICC, 2005)

Design considerations for 2nd-order and 3rd-order bang-bang CDR loops. - Shoujun Wang; Haitao Mei 002; Mashkoor Baig; William Bereza; Tadeusz Kwasniewski; Rakesh H. Patel (CICC, 2005)

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs. - Rakesh H. Patel; William Bereza (CICC, 2006)

PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. - William Bereza; Yuming Tao; Shoujun Wang; Tad A. Kwasniewski; Rakesh H. Patel (DAC, 2006)

Evolving into Embedded Develop. - Matt Fletcher; William Bereza; Mike Karlesky; Greg Williams (AGILE, 2007)

Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A. - Walter Fergusson; Rakesh H. Patel; William Bereza (CICC, 2007)

Nonlinear behavior study in digital bang-bang PLL. - Albert Vareljian; Mohsen Moussavi; William Bereza; Walter Fergusson; Charles E. Berndt; Rakesh H. Patel (CICC, 2009)