Self-Testing of Multichip Logic Modules. - Paul H. Bardell; William H. McAnney (ITC, 1982)

Parallel Pseudorandom Sequences for Built-In Test. - Paul H. Bardell; William H. McAnney (ITC, 1984)

Random Testing for Stuck-At Storage Cells in an Embedded Memory. - William H. McAnney; Paul H. Bardell; V. P. Gupta (ITC, 1984)

Self-Test of Random Access Memories. - Paul H. Bardell; William H. McAnney (ITC, 1985)

Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory. - Jacob Savir; William H. McAnney; Salvatore R. Vecchio (ITC, 1985)

Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory. - Jacob Savir; William H. McAnney; Salvatore R. Vecchio (ITC, 1985)

Pseudorandom Arrays for Built-In Tests. - Paul H. Bardell; William H. McAnney (IEEE Trans. Computers, 1986)

Fault Propagation Through Embedded Multiport Memories. - Jacob Savir; William H. McAnney; Salvatore R. Vecchio (IEEE Trans. Computers, 1987)

Identification of Failing Tests with Cycling Registers. - Jacob Savir; William H. McAnney (ITC, 1988)

Built-in test for RAMs. - Paul H. Bardell; William H. McAnney (IEEE Des. Test, 1988)

Built-In Checking of the Correct Self-Test Signature. - William H. McAnney; Jacob Savir (IEEE Trans. Computers, 1988)

Random Pattern Testability of Delay Faults. - Jacob Savir; William H. McAnney (IEEE Trans. Computers, 1988)

Testing for Coupled Cells in Random-Access Memories. - Jacob Savir; William H. McAnney; Salvatore R. Vecchio (IEEE Trans. Computers, 1991)

A Multiple Seed Linear Feedback Shift Register. - Jacob Savir; William H. McAnney (IEEE Trans. Computers, 1992)