Real-Time Trace Generation. - David R. Kaeli; O. Richard LaMaire; Peter P. Hennet; William W. White; William J. Starke (Int. J. Comput. Simul., 1996)

IBM POWER6 microarchitecture. - Hung Q. Le; William J. Starke; J. Stephen Fields; Francis P. O'Connell; Dung Q. Nguyen; Bruce J. Ronchetti; Wolfram Sauer; Eric M. Schwarz; Michael T. Vaden (IBM J. Res. Dev., 2007)

POWER7: IBM's next generation, balanced POWER server chip. - William J. Starke (Hot Chips Symposium, 2009)

The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor. - Dieter F. Wendel; Ronald N. Kalla; Robert Cargnoni; Joachim G. Clabes; Joshua Friedrich; Roland Frech; James A. Kahle; Balaram Sinharoy; William J. Starke; Scott A. Taylor; Steve Weitzel; Sam G. Chu; et al. (ISSCC, 2010)

Power7: IBM's Next-Generation Server Processor. - Ronald N. Kalla; Balaram Sinharoy; William J. Starke; Michael S. Floyd (IEEE Micro, 2010)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)

The POWER8TM processor: Designed for big data, analytics, and cloud environments. - Joshua Friedrich; Hung Q. Le; William J. Starke; Jeff Stuecheli; Balaram Sinharoy; Eric J. Fluhr; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; David Hogenmiller; Frank Malgioglio; et al. (ICICDT, 2014)

Transactional memory support in the IBM POWER8 processor. - Hung Q. Le; Guy L. Guthrie; Derek Williams; Maged M. Michael; Brad Frey; William J. Starke; Cathy May; Rei Odaira; Takuya Nakaike (IBM J. Res. Dev., 2015)

The cache and memory subsystems of the IBM POWER8 processor. - William J. Starke; Jeffrey Stuecheli; David Daly; J. S. Dodson; Florian Auernhammer; Patricia Sagmeister; Guy L. Guthrie; Charles F. Marino; M. S. Siegel; Bart Blaner (IBM J. Res. Dev., 2015)

IBM Power9 Processor Architecture. - Satish Kumar Sadasivam; Brian W. Thompto; Ronald N. Kalla; William J. Starke (IEEE Micro, 2017)

IBM POWER9 memory architectures for optimized systems. - William J. Starke; J. S. Dodson; Jeffrey Stuecheli; Eric Retter; Brad W. Michael; Stephen J. Powell; James A. Marcella (IBM J. Res. Dev., 2018)

IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI. - Jeffrey Stuecheli; William J. Starke; John D. Irish; L. Baba Arimilli; Daniel M. Dreps; Bart Blaner; Curt Wollbrink; Brian Allison (IBM J. Res. Dev., 2018)

IBM's Next Generation POWER Processor. - Jeff Stuecheli; Scott Willenborg; William J. Starke (Hot Chips Symposium, 2019)

IBM's POWER10 Processor. - William J. Starke; Brian W. Thompto (Hot Chips Symposium, 2020)

Data Compression Accelerator on IBM POWER9 and z15 Processors : Industrial Product. - Bülent Abali; Bart Blaner; John J. Reilly; Matthias Klein; Ashutosh Mishra; Craig B. Agricola; Bedri Sendir; Alper Buyuktosunoglu; Christian Jacobi 002; William J. Starke; Haren Myneni; Charlie Wang (ISCA, 2020)

Energy Efficiency Boost in the AI-Infused POWER10 Processor. - Brian W. Thompto; Dung Q. Nguyen; José E. Moreira; Ramon Bertran; Hans M. Jacobson; Richard J. Eickemeyer; Rahul M. Rao; Michael Goulet; Marcy Byers; Christopher J. Gonzalez; Karthik Swaminathan; Nagu R. Dhanwada; et al. (ISCA, 2021)

IBM's POWER10 Processor. - William J. Starke; Brian W. Thompto; Jeffrey Stuecheli; José E. Moreira (IEEE Micro, 2021)