Asynchronous Macrocell Interconnect using MARBLE. - W. J. Bainbridge; Stephen B. Furber (ASYNC, 1998)

AMULET3i - An Asynchronous System-on-Chip. - Jim D. Garside; W. J. Bainbridge; Andrew Bardsley; David M. Clark; David A. Edwards; Stephen B. Furber; David W. Lloyd; Siamak Mohammadi; J. S. Pepper; Steve Temple; John V. Woods; Jianwei Liu; et al. (ASYNC, 2000)

MARBLE: an asynchronous on-chip macrocell bus. - W. J. Bainbridge; Stephen B. Furber (Microprocess. Microsystems, 2000)

Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. - W. J. Bainbridge; Stephen B. Furber (ASYNC, 2001)

SPA - A Synthesisable Amulet Core for Smartcard pplications. - W. J. Bainbridge; Andrew Bardsley; Steve Temple; Jim D. Garside; Peter A. Riocreux; Luis A. Plana (ASYNC, 2002)

Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes. - W. J. Bainbridge; William B. Toms; David A. Edwards; Stephen B. Furber (ASYNC, 2003)

SPA - a secure Amulet core for smartcard applications. - Luis A. Plana; Peter A. Riocreux; W. J. Bainbridge; Andrew Bardsley; Steve Temple; Jim D. Garside; Z. C. Yu (Microprocess. Microsystems, 2003)

The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. - W. J. Bainbridge; Luis A. Plana; Stephen B. Furber (DATE, 2004)

Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links. - William John Bainbridge; Sean James Salisbury (ASYNC, 2009)

Area efficient asynchronous SDM routers using 2-stage Clos switches. - Wei Song 002; Doug A. Edwards; Jim D. Garside; William J. Bainbridge (DATE, 2012)