The effect of page allocation on caches. - William L. Lynch; Brian K. Bray; Michael J. Flynn (MICRO, 1992)

Low Load Latency Through Sum-Addressed Memory (SAM). - William L. Lynch; Gary Lauterbach; Joseph I. Chamdani (ISCA, 1998)

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. - Raymond A. Heald; Ken Shin; Vinita Reddy; I-Feng Kao; Masood Khan; William L. Lynch; Gary Lauterbach; Joe Petolino (IEEE J. Solid State Circuits, 1998)