Design SRAMs for burn-in. - William R. Reohr; Yuen H. Chan; Donald W. Plass; Antonio Pelella; Philip T. Wu (VTS, 1993)

A high-speed 128-kb MRAM core for future universal memory applications. - John K. DeBrosse; Dietmar Gogl; Alexander Bette; Heinz Hoenigschmid; Raphael Robertazzi; Christian Arndt; Daniel Braun 011; D. Casarotto; Robert Havreluk; Stefan Lammers; Werner Obermaier; William R. Reohr; et al. (IEEE J. Solid State Circuits, 2004)

Memories: Exploiting Them and Developing Them. - William R. Reohr (SoCC, 2006)

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (ISSCC, 2007)

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. - Jente B. Kuang; Abraham Mathews; John Barth 001; Fadi H. Gebara; Tuyet Nguyen; Jeremy D. Schaub; Kevin J. Nowka; Gary D. Carpenter; Don Plass; Erik Nelson; Ivan Vo; William R. Reohr; et al. (ESSCIRC, 2008)

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (IEEE J. Solid State Circuits, 2008)

Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications. - Philip G. Emma; William R. Reohr; Mesut Meterelliyoz (IEEE Micro, 2008)

Statistical yield analysis of silicon-on-insulator embedded DRAM. - Rouwaida Kanj; Rajiv V. Joshi; Jente B. Kuang; J. Kim; Mesut Meterelliyoz; William R. Reohr; Sani R. Nassif; Kevin J. Nowka (ISQED, 2009)

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. - Peter J. Klim; John Barth 001; William R. Reohr; David Dick; Gregory Fredeman; Gary Koch; Hien M. Le; Aditya Khargonekar; Pamela Wilcox; John Golz; Jente B. Kuang; Abraham Mathews; et al. (IEEE J. Solid State Circuits, 2009)

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. - John Barth 001; Don Plass; Erik Nelson; Charlie Hwang; Gregory Fredeman; Michael A. Sperling; Abraham Mathews; William R. Reohr; Kavita Nair; Nianzheng Cao (ISSCC, 2010)

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. - John Barth 001; Don Plass; Erik Nelson; Charlie Hwang; Gregory Fredeman; Michael A. Sperling; Abraham Mathews; Toshiaki Kirihata; William R. Reohr; Kavita Nair; Nianzheng Cao (IEEE J. Solid State Circuits, 2011)