Rigel: an architecture and scalable programming interface for a 1000-core accelerator. - John H. Kelm; Daniel R. Johnson; Matthew R. Johnson 003; Neal Clayton Crago; William Tuohy; Aqeel Mahesri; Steven S. Lumetta; Matthew I. Frank; Sanjay J. Patel (ISCA, 2009)

GoldMine: Automatic assertion generation using data mining and static analysis. - Shobha Vasudevan; David Sheridan; Sanjay J. Patel; David Tcheng; William Tuohy; Daniel R. Johnson (DATE, 2010)

Cohesion: a hybrid memory model for accelerators. - John H. Kelm; Daniel R. Johnson; William Tuohy; Steven S. Lumetta; Sanjay J. Patel (ISCA, 2010)

Towards coverage closure: Using GoldMine assertions for generating design validation stimulus. - Lingyi Liu; David Sheridan; William Tuohy; Shobha Vasudevan (DATE, 2011)

Rigel: A 1, 024-Core Single-Chip Accelerator Architecture. - Daniel R. Johnson; Matthew R. Johnson 003; John H. Kelm; William Tuohy; Steven S. Lumetta; Sanjay J. Patel (IEEE Micro, 2011)

Cohesion: An Adaptive Hybrid Memory Model for Accelerators. - John H. Kelm; Daniel R. Johnson; William Tuohy; Steven S. Lumetta; Sanjay J. Patel (IEEE Micro, 2011)

A Technique for Test Coverage Closure Using GoldMine. - Lingyi Liu; David Sheridan; William Tuohy; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Improving Energy and Performance with Spintronics Caches in Multicore Systems. - William Tuohy; Cong Ma; Pushkar Nandkar; Nishant Borse; David J. Lilja (Euro-Par Workshops (2), 2014)

Impact of spintronic memory on multicore cache hierarchy design. - Cong Ma; William Tuohy; David J. Lilja (IET Comput. Digit. Tech., 2017)