A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File. - Nestoras Tzartzanis; William W. Walker (ICCD, 2003)

An efficient transistor optimizer for custom circuits. - Xiao Yan Yu; Vojin G. Oklobdzija; William W. Walker (ISCAS (5), 2003)

Analysis techniques for obtaining the steady-state solution of MOS LC oscillators. - Makram M. Mansour; Amit Mehrotra; William W. Walker; Amit Narayan (ISCAS (5), 2004)

A test circuit for measurement of clocked storage element characteristics. - Nikola Nedovic; William W. Walker; Vojin G. Oklobdzija (IEEE J. Solid State Circuits, 2004)

A sliding window scheme for accurate clock mesh analysis. - Hongyu Chen; Chao-Yang Yeh; Gustavo R. Wilke; Subodh M. Reddy; Hoa-van Nguyen; William W. Walker; Rajeev Murgai (ICCAD, 2005)

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. - Yusuke Okaniwa; Hirotaka Tamura; Masaya Kibune; Daisuke Yamazaki; Tsz-Shing Cheung; Junji Ogawa; Nestoras Tzartzanis; William W. Walker; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. - Yasumoto Tomita; Masaya Kibune; Junji Ogawa; William W. Walker; Hirotaka Tamura; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

Differential current-mode sensing for efficient on-chip global signaling. - Nestoras Tzartzanis; William W. Walker (IEEE J. Solid State Circuits, 2005)

A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing. - Hisashige Ando; Nestoras Tzartzanis; William W. Walker (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers. - Ricky Yuen; Marcus van Ierssel; Ali Sheikholeslami; William W. Walker; Hirotaka Tamura (CICC, 2006)

Clock Distribution Architectures: A Comparative Study. - Chao-Yang Yeh; Gustavo R. Wilke; Hongyu Chen; Subodh M. Reddy; Hoa-van Nguyen; Takashi Miyoshi; William W. Walker; Rajeev Murgai (ISQED, 2006)

A 3.2Gb/s Semi-Blind-Oversampling CDR. - Marcus van Ierssel; Ali Sheikholeslami; Hirotaka Tamura; William W. Walker (ISSCC, 2006)

A Reversible Poly-Phase Distributed VCO. - Nestoras Tzartzanis; William W. Walker (ISSCC, 2006)

A Case Study: Energy Efficient High Throughput Chip Multi-Processor Using Reduced-complexity Cores for Transaction Processing Workload. - Hisashige Ando; Akira Asato; Motoyuki Kawaba; Hideki Okawara; William W. Walker (Inf. Media Technol., 2006)

A 40-to-44Gb/s 3? Oversampling CMOS CDR/1: 16 DEMUX. - Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker (ISSCC, 2007)

An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. - Vineet Wason; Rajeev Murgai; William W. Walker (VLSI Design, 2007)

A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance. - Marcus van Ierssel; Ali Sheikholeslami; Hirotaka Tamura; William W. Walker (IEEE J. Solid State Circuits, 2007)

A Leakage Current Replica Keeper for Dynamic Circuits. - Yolin Lih; Nestoras Tzartzanis; William W. Walker (IEEE J. Solid State Circuits, 2007)

A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. - Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker (IEEE J. Solid State Circuits, 2007)

Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI. - Marcus van Ierssel; Hisakatsu Yamaguchi; Ali Sheikholeslami; Hirotaka Tamura; William W. Walker (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (ISSCC, 2009)

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (IEEE J. Solid State Circuits, 2009)

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. - Nikola Nedovic; Anders Kristensson; Samir Parikh; Subodh M. Reddy; Scott McLeod; Nestoras Tzartzanis; Kouichi Kanda; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Satoshi Ide; et al. (IEEE J. Solid State Circuits, 2010)

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. - Yasuo Hidaka; Takeshi Horie; Yoichi Koyanagi; Takashi Miyoshi; Hideki Osone; Samir Parikh; Subodh M. Reddy; Toshiyuki Shibuya; Yasushi Umezawa; William W. Walker (ISSCC, 2011)

A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. - Samir Parikh; Tony Kao; Yasuo Hidaka; Jian Jiang; Asako Toda; Scott McLeod; William W. Walker; Yoichi Koyanagi; Toshiyuki Shibuya; Jun Yamada (ISSCC, 2013)