Approximate timing analysis of combinational circuits under the XBD0 model. - Yuji Kukimoto; Wilsin Gosti; Alexander Saldanha; Robert K. Brayton (ICCAD, 1997)

Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions. - Rajeev K. Ranjan 001; Wilsin Gosti; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1997)

An Exact Input Encoding Algorithm for BDDs Representing FSMs. - Wilsin Gosti; Alberto L. Sangiovanni-Vincentelli; Tiziano Villa; Alexander Saldanha (Great Lakes Symposium on VLSI, 1998)

Wireplanning in logic synthesis. - Wilsin Gosti; Amit Narayan; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1998)

Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. - Wilsin Gosti; Sunil P. Khatri; Alberto L. Sangiovanni-Vincentelli (ICCAD, 2001)

FSM Encoding for BDD Representations. - Wilsin Gosti; Tiziano Villa; Alexander Saldanha; Alberto L. Sangiovanni-Vincentelli (Int. J. Appl. Math. Comput. Sci., 2007)

Postplacement voltage assignment under performance constraints. - Huaizhi Wu; Martin D. F. Wong; Wilsin Gosti (ACM Trans. Design Autom. Electr. Syst., 2008)