Analysis of matrix multiplication on high density Virtex-7 FPGA. - Wilson José; Ana Rita Silva; Horácio C. Neto; Mário P. Véstias (FPL, 2013)

Design of a massively parallel computing architecture for dense matrix multiplication. - Wilson José; Ana Rita Silva; Mário P. Véstias; Horácio C. Neto (LASCAS, 2013)

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. - Wilson José; Ana Rita Silva; Horácio C. Neto; Mário P. Véstias (FPL, 2014)

Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture. - João Pinhão; Wilson José; Horácio C. Neto; Mário P. Véstias (DSD, 2015)