Feedforward compensation technique for all digital phase locked loop based synthesizers. - Win Chaivipas; Akira Matsuzawa; Philipus Chandra Oh (ISCAS, 2006)

Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop. - Win Chaivipas; Akira Matsuzawa (IEICE Trans. Electron., 2007)

A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter. - Philipus Chandra Oh; Akira Matsuzawa; Win Chaivipas (IEICE Trans. Electron., 2007)

Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators. - Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2008)

Analysis of CMOS Transconductance Amplifiers for Sampling Mixers. - Ning Li 009; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2008)

A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique. - Ahmed Musa; Rui Murakami; Takahiro Sato; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2011)

A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c. - Kenichi Okada 001; Kota Matsushita; Keigo Bunsen; Rui Murakami; Ahmed Musa; Takahiro Sato; Hiroki Asada; Naoki Takayama; Ning Li 009; Shogo Ito; Win Chaivipas; Ryo Minami; et al. (ISSCC, 2011)

A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications. - Ahmed Musa; Rui Murakami; Takahiro Sato; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2011)

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c. - Kenichi Okada 001; Ning Li 009; Kota Matsushita; Keigo Bunsen; Rui Murakami; Ahmed Musa; Takahiro Sato; Hiroki Asada; Naoki Takayama; Shogo Ito; Win Chaivipas; Ryo Minami; et al. (IEEE J. Solid State Circuits, 2011)

A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS. - Ryo Minami; Hiroki Asada; Ahmed Musa; Takahiro Sato; Ning Li 009; Tatsuya Yamaguchi; Yasuaki Takeuchi; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2012)

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. - Yoshiyasu Doi; Takayuki Shibasaki; Takumi Danjo; Win Chaivipas; Takushi Hashida; Hiroki Miyaoka; Masanori Hoshino; Yoichi Koyanagi; Takuji Yamamoto; Sanroku Tsukamoto; Hirotaka Tamura (ISSCC, 2013)

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. - Yoshiyasu Doi; Takayuki Shibasaki; Takumi Danjo; Win Chaivipas; Takushi Hashida; Hiroki Miyaoka; Masanori Hoshino; Yoichi Koyanagi; Takuji Yamamoto; Sanroku Tsukamoto; Hirotaka Tamura (IEEE J. Solid State Circuits, 2013)

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. - Takayuki Shibasaki; Win Chaivipas; Yanfei Chen; Yoshiyasu Doi; Takayuki Hamada; Hideki Takauchi; Toshihiko Mori; Yoichi Koyanagi; Hirotaka Tamura (VLSIC, 2014)