A Hierarchical Multiprocessor Achitecture for Video Coding Applications. - Peter Pirsch; Winfried Gehrke; Richard Hoffer (ISCAS, 1993)

VLSI chip set for 2D HDTV subband filtering with on-chip line memories. - Marco Winzker; Klaus Grüger; Winfried Gehrke; Peter Pirsch (IEEE J. Solid State Circuits, 1993)

A hierarchical multiprocessor architecture based on heterogeneous processors for video coding applications. - Winfried Gehrke; Richard Hoffer; Peter Pirsch (ICASSP (2), 1994)

Associative controlling of monolithic parallel processor architectures. - Winfried Gehrke; Klaus Gaedke (IEEE Trans. Circuits Syst. Video Technol., 1995)

Assoziatives Controlling von programmierbaren Parallelprozessoren für die Videosignalverarbeitung. - Winfried Gehrke (VDI-Verlag, 1996)

A flexible, fully configurable architecture for MPEG-2 video encoding. - Jörn Jachalsky; M. Wahle; Peter Pirsch; Winfried Gehrke (ICECS, 2002)

A core for ambient and mobile intelligent imaging applications. - Jörn Jachalsky; Martin Wahler; Peter Pirsch; S. Capperon; Winfried Gehrke; W. M. Kruijtzer; Antonio Núñez (ICME, 2003)

The design of a smart imaging core for automotive and consumer applications: a case study. - Wido Kruijtzer; Winfried Gehrke; Víctor Reyes; Ghiath Alkadi; Thomas Hinz; Jörn Jachalsky; Bruno Steux (CODES+ISSS, 2005)

Design, synthesis and verification of a smart imaging core using SystemC. - Wido Kruijtzer; Víctor Reyes; Winfried Gehrke (Des. Autom. Embed. Syst., 2005)

A Highly Parallel Sub-Pel Accurate Motion Estimator for H.264. - Sebastian Flügel; Heiko Klußmann; Peter Pirsch; Marco Schulz; Malik Cisse; Winfried Gehrke (MMSP, 2006)

Scalable Multi-Standard LSI Texture Encoder for MPEG and VC-1 Video Compression. - Norman Nolte; Winfried Gehrke; Frank Wiczinowski; Peter Pirsch (ICME, 2007)