8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm. - Danfeng Xu; Yu Kou; Paul Lai; Zichuan Cheng; Tze Yin Cheung; Larry Moser; Yang Zhang; Xiaolong Liu; Man Pio Lam; Haikun Jia; Quan Pan 002; Wing Hong Szeto; et al. (ISSCC, 2021)