Hierarchial global wiring for custom chip design. - Wing K. Luk; Donald T. Tang; C. K. Wong (DAC, 1986)

Constructing Maximal Slicings from Geometry. - Markku Tamminen; Wing K. Luk; Paolo Sipala; Lin S. Woo; C. K. Wong (Acta Informatica, 1986)

Minimum-Area Wiring for Slicing Structures. - Wing K. Luk; Paolo Sipala; C. K. Wong (IEEE Trans. Computers, 1987)

A Hierarchical Global Wiring Algorithm for Custom Chip Design. - Wing K. Luk; Paolo Sipala; Markku Tamminen; Donald T. Tang; Lin S. Woo; Chak-Kuen Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout. - Wing K. Luk; Alvar A. Dean (DAC, 1989)

Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout. - Wing K. Luk; Alvar A. Dean; John W. Mathews (ICCAD, 1989)

Partitioning and floor-planning for data-path chip (microprocessor) layout. - Wing K. Luk; Alvar A. Dean; John W. Mathews (Integr., 1990)

A Fast Physical Constraint Generator for Timing Driven Layout. - Wing K. Luk (DAC, 1991)

Multistack optimization for data-path chip layout. - Wing K. Luk; Alvar A. Dean (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Optimizing rod window width in positron emission tomography. - William F. Jones; Ward M. Digby; Wing K. Luk; Michael E. Casey; Larry G. Byars (IEEE Trans. Medical Imaging, 1995)

A novel dynamic memory cell with internal voltage gain. - Wing K. Luk; Robert H. Dennard (IEEE J. Solid State Circuits, 2005)

Gated-diode amplifiers. - Wing K. Luk; Robert H. Dennard (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A compact low-power 3D I/O in 45nm CMOS. - Yong Liu 023; Wing K. Luk; Daniel J. Friedman (ISSCC, 2012)

POWER8 design methodology innovations for improving productivity and reducing power. - Matthew M. Ziegler; Ruchir Puri; Bob Philhower; Robert L. Franch; Wing K. Luk; Jens Leenstra; Peter Verwegen; Niels Fricke; George Gristede; Eric Fluhr; Victor V. Zyuban (CICC, 2014)