A dual-MST approach for clock network synthesis. - Jingwei Lu; Wing-Kai Chow; Chiu-Wing Sham; Evangeline F. Y. Young (ASP-DAC, 2010)

Clock Network Synthesis with Concurrent Gate Insertion. - Jingwei Lu; Wing-Kai Chow; Chiu-Wing Sham (PATMOS, 2010)

A new clock network synthesizer for modern VLSI designs. - Jingwei Lu; Wing-Kai Chow; Chiu-Wing Sham (Integr., 2012)

Fast Power- and Slew-Aware Gated Clock Tree Synthesis. - Jingwei Lu; Wing-Kai Chow; Chiu-Wing Sham (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Ripple 2.0: high quality routability-driven placement via global router integration. - Xu He; Tao Huang 016; Wing-Kai Chow; Jian Kuang 001; Ka-Chun Lam; Wenzan Cai; Evangeline F. Y. Young (DAC, 2013)

SRP: simultaneous routing and placement for congestion refinement. - Xu He; Wing-Kai Chow; Evangeline F. Y. Young (ISPD, 2013)

Triple patterning lithography aware optimization for standard cell based design. - Jian Kuang 001; Wing-Kai Chow; Evangeline F. Y. Young (ICCAD, 2014)

Cell density-driven detailed placement with displacement constraint. - Wing-Kai Chow; Jian Kuang 001; Xu He; Wenzan Cai; Evangeline F. Y. Young (ISPD, 2014)

Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach. - Wing-Kai Chow; Liang Li; Evangeline F. Y. Young; Chiu-Wing Sham (Integr., 2014)

A robust approach for process variation aware mask optimization. - Jian Kuang 001; Wing-Kai Chow; Evangeline F. Y. Young (DATE, 2015)

Legalization algorithm for multiple-row height standard cell design. - Wing-Kai Chow; Chak-Wa Pui; Evangeline F. Y. Young (DAC, 2016)

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. - Chak-Wa Pui; Gengjie Chen; Wing-Kai Chow; Ka-Chun Lam; Jian Kuang 001; Peishan Tu; Hang Zhang 010; Evangeline F. Y. Young; Bei Yu 001 (ICCAD, 2016)

Placement: From Wirelength to Detailed Routability. - Wing-Kai Chow; Evangeline F. Y. Young (IPSJ Trans. Syst. LSI Des. Methodol., 2016)

Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs. - Jian Kuang 001; Wing-Kai Chow; Evangeline F. Y. Young (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Fence-aware detailed-routability driven placement. - Wing-Kai Chow; Jian Kuang 001; Peishan Tu; Evangeline F. Y. Young (SLIP, 2017)

Timing driven routing tree construction. - Peishan Tu; Wing-Kai Chow; Evangeline F. Y. Young (SLIP, 2017)

Routability-driven and fence-aware legalization for mixed-cell-height circuits. - Haocheng Li; Wing-Kai Chow; Gengjie Chen; Evangeline F. Y. Young; Bei Yu 001 (DAC, 2018)

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. - Charles J. Alpert; Wing-Kai Chow; Kwangsoo Han; Andrew B. Kahng; Zhuo Li 001; Derong Liu 002; Sriram Venkatesh (ISPD, 2018)

ISPD 2018 Initial Detailed Routing Contest and Benchmarks. - Stefanus Mantik; Gracieli Posser; Wing-Kai Chow; Yixiao Ding; Wen-Hao Liu 001 (ISPD, 2018)

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. - Gengjie Chen; Chak-Wa Pui; Wing-Kai Chow; Ka-Chun Lam; Jian Kuang 001; Evangeline F. Y. Young; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. - Wen-Hao Liu 001; Stefanus Mantik; Wing-Kai Chow; Yixiao Ding; Amin Farshidi; Gracieli Posser (ISPD, 2019)

Pin-Accessible Legalization for Mixed-Cell-Height Circuits. - Haocheng Li; Wing-Kai Chow; Gengjie Chen; Bei Yu 001; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)